JPS6247900A - Memory device - Google Patents

Abstract

PURPOSE:To obtain a memory device having high reliability by providing a data selector to select one bit out of the multi-bit width of a DRAM and performing the transfer of data from and to an ECC for each data word consisting of said selected bit. CONSTITUTION:In an access mode, address signals are applied to all DRAMs 4C0-4D7 and selection designating signals are supplied equally to all data selectors 2C0-2D7 and 3C0-3D7 from a driver 5. Thus a single piece of word data on the same output terminal is selected. This selected data word of a bit is used as a single unit for transfer of data between an ECC 1 and the DRAMs 4C0-4D7 respectively. In a write mode with correction of errors, all selectors 2C0-2D7 are enabled for the signal of a driver 6. Thus the data words are written on the memories 4D0-4D7 via the selectors 2D0-2D7 and the redundant words are written on memories 4C0-4C5 via selectors 2C0-2C5 respectively. In a read mode, all selectors 3C0-3D7 are enabled by a driver 7. Then the data words and redundant data words are read out via selectors 3D0-3D7 and 3C0-3C5 respectively. In such constitution, it is possible to obtain a memory device that is free from burst error with high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory device, and particularly to a DR having a multi-bit width configuration.
The present invention relates to a memory device using AM.

[Technical background of the invention and its problems]

Multiple dynamic random access memories (DRAMs)
), when one DRAM fails and it can be detected as a single-bit data error, the 1-bit error data is automatically corrected, and 2.
Conventionally, an error correction circuit (hereinafter referred to as FCC) has been used to detect a bit error.

In this case, the conventional DRAM is, for example, 16K x 1 bit,
DRAM with 1 bit width configuration such as 256K x 1 bit
Therefore, it was relatively easy to configure a memory device with an FCC function. However, in recent years 256K
This has become difficult in DRAMs with multi-bit width configurations such as X4 bits, 64KX8 bits, and 64KX4 bits.

This will be explained in detail below with reference to FIG.

FIG. 2 is a circuit diagram showing a conventional example of a memory device constructed using these multi-bit width DRAMs. Second
In the circuit shown in the figure, a DRAM12a with a 4-bit width configuration is used.
~12d is connected to the ECC 11, and a memory address is designated by the driver 13, so that each memory has an automatic π pressure function. Therefore, the data input/output bit of the DRAM 12a is the redundant bit terminal C8 of the ECC 11.
, C1, and the data input/output bits of the DRAM 12b are connected to redundant bit terminals C2 to C5. Also, D
The data input/output bits of RAM12c go to data bit terminals D-D3, and those of DRAM12d go to terminals D-D.
7 respectively.

In this way, if a DRAM with a multi-bit width configuration is configured to have an FCC function using the conventional method, for example, if one DRAM 12d fails, this DRAM
Multiple bits of data held by RAMl 2d, ie D4
~D7 becomes a burst error all at once. At this time, the conventional ECC 11, which has a 1-bit error automatic correction function and a 2-bit error detection function, cannot perform error correction or detection.

Also, if you try to enable correction or detection, ECC11
had the disadvantage of requiring a huge number of redundant bits.

[Purpose of the invention]

The present invention has been made in order to eliminate the drawbacks of the above-mentioned prior art, and provides a memory device that has an error detection and correction function with a simple configuration even when using a DRAM with a multi-bit width configuration. The purpose is to

[Summary of the invention]

In order to achieve the above object, the present invention provides an error correction circuit that automatically corrects 1-bit error data, a plurality of DRAMs each having a multi-bit width, and an error correction circuit that automatically corrects 1-bit error data, A plurality of data selectors for selecting one bit are provided, and data is exchanged between the error correction circuit and the DRAM in units of data words each consisting of one bit selected by the plurality of data selectors. The present invention provides a memory device.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to FIG.

FIG. 1 is a circuit diagram showing the configuration of a memory device according to an embodiment. ECC1 is 8+6=14 DRAM4~4
When a data error COC5, DO07 occurs in L4-4, it has a function of automatically correcting the erroneous bit and outputting correct data. In this embodiment as well, a 4-bit width configuration is used as the DRAM 4 co to 4, 7, but the present invention is not limited to a 4-bit width configuration. FCCl redundant bit terminals C, C...C5 and data bit terminals. , Dl・
...The data input terminals of data selectors 2°0 to 207 and the data output terminals of data selectors 3°0 to 3,7 are connected to D7, respectively, and the data output terminals of these data selectors 2°0 to 2,7 are connected to D7. Terminal and data selector 3
The data input terminals ゜0 to 307 are each DRA
It is connected to the data input/output terminal C-D7 of M4co~407.

Data selectors 2°0 to 207 operate when writing to memory, and data selectors 3°0 to 307 operate when reading from memory. Data selector 2-2 3-3
The control signal that selects and specifies 1 bit of the 4-bit COD7-C007 data that is input and output is the driver 5.
is output from. DRAM4oo~4 during error correction,
A driver 6 for outputting a write permission signal for 7 is connected to data selectors 2゜0 to 207, and a driver 7 for outputting a read permission signal for error detection and correction is connected to data selectors 3゜0 to 3D7. has been done. Further, an address driver 8 for specifying read/write addresses for the DRAMs 4co to 407 is connected to address terminals of the DRAMs 4co to 4 and 7. Data selector 2゜0~2g7J3 and 3゜0~
By adopting the configuration shown in FIG. 1, 3o7 has the configuration shown in FIG.
It has a function of selecting one bit of each 4-bit wide output data of RAM 4co to 4D7.

Next, the operation of the circuit shown in FIG. 1 will be explained.

At the time of memory access, the driver 8 outputs address signals to all of the DRAMs 4oo to 4 and 7. The signal that controls the selection of 1 bit of the 4-bit input/output data of each D R'A M 4co to 4, 7 is the driver 5.
The signal is output from the data selector 2CO-2 and 3°0-3D7. That is, the selection designation signal from the driver 5 is equally input to all data selectors 2.degree. 0 to 2D7 and 3.degree. 0 to 3D7, thereby selecting one word data of the same output terminal. The data word consisting of the selected 1 bit is sent as a unit to E'CC1 and DRAM4Co~4.
Data is exchanged with D7.

During a write operation of error correction data, a write enable signal is output from the driver 6 to the data selectors 2.0 to 2D7, and all of the data selectors 2.0 to 2.07 are enabled. As a result, from ECC1 to DRAM4
Data words and redundancy words are written to oo-4o7. That is, data words are written to DRAMs 4oo to 4o7 via data selectors 2Do to 2D7, and data words are written to DRAMs 4oo to 4o7 via data selectors 2Do to 2D7.
Redundant words are written in 4 co to 4 cs.

During the output operation to the ECC1 by memory read, the read permission signal from the driver 7 is sent to the data selector 3°0~3.
Output to D7, data selector 3°0 to 3D7
All are enabled. This allows the DRAM
1 at the same output position for ECC1 from 4co~4,7
A set of data words and redundancy words will be read. That is, the data word is read out via the data selectors 3°0 to 3D7, and the data word is read out via the data selectors 3Co to 3C.
5, the redundant word is read out.

If the circuit configuration shown in FIG. 1 is used, the present invention can be applied not only to a 4-bit wide DRAM, but also to any DRAM of any bit width in principle.

〔Effect of the invention〕

As explained above, in the present invention, DR of multi-bit width depiction
Even if AM is used, a data selector that selects one bit from the bit width of this DRAM is provided, and data can be exchanged with the FCC in units of data words consisting of the selected one bit. Since the structure is configured to perform this, a highly reliable memory device with a correctly functioning FCC can be realized without causing a burst error even when a DRAM having multiple pitches and widths is used.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a memory device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a memory device configured using a conventional method using a DRAM having a multi-bit width. 1...Error correction circuit (FCC), 2Co~2C5゜2
~2...Data selector 3~33DOD7
)Co C3-DO~3D7"・Data selector, 4Co~4o5, 4oo~"D7...D
RAM, 5... A driver that outputs a control signal for the data selector, 6... A driver that outputs a write permission signal, 7... A driver that outputs a read permission signal.
8...Driver that outputs memory address.

Claims (1)

[Claims] an error correction circuit that automatically corrects 1-bit error data;
Multiple DRAMs with multi-bit width and these multiple DRAMs
and a plurality of data selectors for selecting one bit of the input/output data of a plurality of bit widths possessed by the plurality of data selectors, and the error correction circuit uses a data word constituted by one bit selected by the plurality of data selectors as a unit. and the above D
A memory device that exchanges data with RAM.