JPS624799B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bidirectional shift register suitable for integrated circuits.

In general, shift registers are circuits that are very often used for data retention, delay, etc. in digital integrated circuits. For example, if you want to convert data to binary and transfer it to bit serial,
Used as a timing alignment circuit. In this case, if the data is transferred starting from the least significant digit and ending at the most significant digit, inserting a 1-bit delay means that the carry is carried up by one digit compared to not inserting this delay. In other words, it is multiplied by "2". On the other hand, when looking at the data with the delay inserted, the data without the delay has been downgraded by one digit, and is thus the data divided by "2". In this way, data obtained by delaying certain data by 1 bit is multiplied by 2, and data obtained by advancing 1 bit becomes data divided by 2. In this way, data can be doubled, 2 ² times, 2 ³ times, etc., or 1/2, 1/2
If you want to do ² , 1/2 ³ , etc., it would be very convenient to have a bidirectional shift register.

Such a conventional bidirectional shift register had a circuit configuration as shown in FIG. In addition,
In this example, the shift register configuration is for 4 bits. That is, data transfer for each bit is performed by D-type flip-flops 1, 2, 3, and 4 in synchronization with the clock pulse CP, and AND circuits 5 and 6 are connected to the input sides of each flip-flop 1, 2, 3, and 4. An OR circuit 7 is connected. Switching between the right shift and the left shift is performed by the switching signal R/, and when this switching signal R/ is "1", the right shift operation is performed, and the data input from the right shift data input terminal I _R is shifted to the right. The shift data is transferred to the output terminal _OR . On the other hand, when the switching signal R/ is "0", a left shift operation is performed, and the data input from the left shift data input terminal I _L is transferred to the left shift data output terminal O _L.

However, in the conventional bidirectional shift register described above, complex gate circuits such as AND, AND, and OR are required on the input side of each flip-flop 1, 2, 3, and 4, and the wiring is not only complicated but also However, in the design and manufacture of integrated circuits, there has been a serious drawback in that wiring and gate circuits lead to an increase in area.

The present invention has been made in view of the above circumstances, and its purpose is to connect the input of one of two clock synchronous logic circuits to the output of the other, and connect a transmission gate to one of the connection ends. By connecting and configuring 1 bit,
The object of the present invention is to provide a bidirectional shift register that can reduce the number of elements and reduce the area on an integrated circuit with an extremely simple circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows one bit of a bidirectional shift register, in which two clock synchronized logic circuits, for example clocked inverters 21 and 22, are connected to each other with one input and the other output connected. Transmission gate 2 at connection end 23
4 are connected to form a circuit for one bit.

The operation in such a configuration will be explained. It is assumed that the transmission gate 24 is turned on when the clock _φ1 input to the gate is "1" and turned off when it is "0". In the case of a right shift in this circuit, data is transferred to the right through transmission gate 24 and one clocked inverter 21. At this time, by setting the clock _φL to "0", the output of the other clocked inverter 22 is in a high impedance state, so that it does not affect the data to be transferred. On the other hand, in the case of a left shift, data is transferred to the left through the other clocked inverter 22 and transmission gate 24. At this time, by setting the clock _φR to "0", the output of one clocked inverter 21 becomes a high impedance state.

FIG. 3 shows an example of a specific circuit configuration of a clocked inverter. That is, the sources and drains of the four field effect transistors 31, 32, 33, and 34 and adjacent transistors are connected, the source of the transistor 31 on one end is connected to the power supply V _DD , and the transistor on the other end is Ground the drain of 34. The gates of the transistors 32 and 33 are connected in common and connected to an input terminal 35, and the source/drain common connection point is connected to an output terminal 36. Therefore, when the clock φ applied to the gate of the transistor 34 is "1", the inverted signal of the input terminal 35 is obtained at the output terminal 36,
When the clock φ is 0'', the output is in a high impedance state.In addition, in the 1-bit bidirectional shift register constructed in this way, one clocked inverter consists of four elements in FIG. There are nine elements in total, so the number of elements used can be small.

By cascading 1-bit bidirectional shift registers constructed and operated in this manner, a bidirectional shift register with an arbitrary number of bits can be constructed. For example, FIG. 4 shows an example of a circuit in which 4 bits are connected in cascade. Note that the same parts as in FIG. 2 will be described with the same reference numerals. That is, 1-bit shift registers having the configuration shown in FIG. 2 are cascade-connected for 4 bits, and a transmission gate 41 is connected to the input terminal for left shifting.
It is configured by connecting. A clock φ2 is applied to the clock gates of _each clocked inverter 21 and 22 via AND gate circuits 42 and 43, and a clock _φ1 is applied to the gate of each transmission gate 24. A clock _φ1 is applied to the gate of the mission gate 41 via an AND circuit 44.

The bidirectional register configured in this manner operates dynamically in synchronization with the two-phase clocks φ ₁ and φ ₂ shown in FIG. Then, the control signal R (see FIG. 5) applied to the AND circuit 42 becomes "1" at the time of right shift, resulting in a right shift operation, and the control signal L (see FIG. 5) applied to the AND circuits 43 and 44 becomes "1". (see FIG. 5) becomes "1" during a left shift, thereby resulting in a left shift operation. Therefore, in FIG. 2, the clocked inverter 2
The clocks φ _R and φ _L input to the fourth
In the figure, the signals are R×φ ₂ and L×φ ₂ (see FIG. 5), respectively. Note that the transmission gate 41 is inserted to synchronize the input signal during left shift with the clock _φ1 .

That is, when shifting to the right, by applying the clock φ ₂ and the control signal R shown in FIG. 5 to the AND circuit 42, the pulse R·φ ₂ shown in FIG. 5 is obtained at the output of the AND circuit 42. , this pulse R· _φ2 is applied to each clocked inverter 21,
21... is applied. As a result, the data input from the right shift data input terminal 45 is sequentially transferred through the shift register, and a transfer input is obtained at the right shift data output terminal 46. On the other hand, when shifting to the left, the data is transferred to the AND circuits 43 and 44. By applying the clocks φ ₁ and φ ₂ and _the control signal L shown in FIG. 5, the pulse L·φ ₂ shown in FIG.
is applied to each clocked inverter 22, 22, . As a result, left shift data input terminal 4
The data input from 7 is sequentially transferred in the opposite direction to the above case, and a transfer output is obtained at the left shift data output terminal 48.

A bidirectional shift register configured in this manner can be realized with an extremely simple circuit configuration consisting of a clocked inverter and a transmission gate. Furthermore, since the transmission gate can be used for both right shifting and left shifting, the number of elements can be reduced. Therefore, the area on the circuit can be significantly reduced.

Note that the transmission gate in the embodiment described above may be constituted by a CMOS circuit consisting of a P-channel MOS-FET and an N-channel MOS-FET. Furthermore, the clock synchronization logic circuit is not limited to a clocked inverter, but may be implemented in other circuits as well. Also, the clock is 2 of φ ₁ and φ ₂ .
Although the case of a phase is given as an example, the function does not change even if a one-phase clock φ is used, and φ is used to correspond to _φ1 , and its inversion is used to correspond to _φ2 .

As detailed above, according to the present invention, one input of two clock synchronized logic circuits is connected to the output of the other, and a transmission gate is connected to one of the connection ends to configure one bit. By doing so, it is possible to provide a bidirectional shift register that can reduce the number of elements and reduce the area on an integrated circuit with an extremely simple circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the configuration of a conventional bidirectional shift register, Figures 2 to 5 show an embodiment of the present invention, and Figure 2 is the configuration of a 1-bit bidirectional shift register. 3 is a configuration diagram showing a specific circuit example of the clocked inverter in FIG. 2, and FIG. 4 is a circuit configuration diagram when the shift registers shown in FIG. 2 are connected in cascade for 4 bits. , FIG. 5 is a timing chart for explaining the operation of FIG. 4. 21, 22...Clocked inverter (clock synchronous logic circuit), 24, 41...Transmission gate, 42, 43, 44...AND circuit.

Claims (1)

[Claims] 1. A bidirectional shift register characterized in that the input of one of two clock synchronous logic circuits is connected to the output of the other, and a transmission gate is connected to one of the connection ends. . 2. The bidirectional shift register according to claim 1, wherein the clock synchronous logic circuit is a clocked inverter. 3. The bidirectional shift register according to claim 1, wherein the transmission gate is constructed of a CMOS circuit.