JPS6248809A - Pll circuit - Google Patents

Abstract

PURPOSE:To attain locking to a stable phase by providing a frequency comparator and a changeover switch so as to apply frequency comparison between a basic clock of an input reproducing signal and an extracted clock thereby controlling the frequency of the extracted clock. CONSTITUTION:The reproduced signal is inputted to a phase comparator 1 and a frequency comparator 4 and the extracted clock generated in a voltage controlled oscillator VCO 3 is inputted similarly to the comparators 1 and 4. When no phase lock is applied in this case, the output of the comparator 1 is outputted at random and the output of the comparator 4 detects whether the reproducing signal is higher or lower than the reproducing signal. In throwing the changeover switch 5 to the position of the comparator 4, the frequency locking loop is closed. As a result, the frequency of the extracted clock generated from the VCO 3 is coincident with the frequency of the reproduction signal. In throwing next the switch 5 to the position of the phase comparator 1, since the frequency is coincident, the state is locked stably to the phase locked state.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a playback device for playing back digital information, such as a digital audio disc player.

2. Description of the Related Art In recent years, as digital information recording media have progressed, the performance of playback devices has been improved.

The conventional technology will be described below with reference to the drawings, taking a digital audio disc as an example.

FIG. 3 shows a part of a digital audio disc playback device. 7 is a disk, 8 is a pickup, 9 is a preamplifier, 10 is a PLL circuit, 11 is a motor control circuit, 12
is the motor.

A reproduction signal read out from the disc using a pickup 8 is converted into a binary signal by a preamplifier 9. This 2
The value signal is input to the motor control circuit 11 and the disk 7
The rotational speed of is detected.

A motor control circuit 11 controls the motor. motor 12
As the rotation speed of the preamplifier 9 changes and the output reproduction signal from the preamplifier 9 enters the capture register of the PLL circuit 1o, the PLL circuit 10 locks in phase, so that the clock extraction is performed and the bit Synchronization is established.

FIG. 4 is a block diagram of the PLL circuit, where 9 is a phase comparator, 2 is a filter, and 3 is a voltage controlled oscillator (hereinafter referred to as VCO).

The reproduced signal and the extracted clock generated by VCO3 are:
The phase is compared by a phase comparator 1, smoothed by a filter 2, and used as a control input signal for VC:03 to control the oscillation frequency of VC03.

Since the phase comparison error is no longer output at the point where the phase of the reproduced signal and the extracted clock match, the oscillation frequency of the VCo 3 is stabilized. This state is a phase locked state.

Problems to be Solved by the Invention However, the capture range of an actual PLL circuit is quite narrow, and motor rotation control accuracy cannot be achieved with very high precision due to motor shaft loss, electrical offset of the control circuit, etc. For this reason, there is a problem in that the PLL circuit may not be able to bring the extracted clock into a phase locked state with the reproduced signal.

In view of the above problems, the present invention provides a PLL circuit that can stably enter a phase-locked state in any case.

Means for Solving the Problems In order to solve the above problems, the PLL circuit of the present invention is provided with a structure of a frequency pull-in loop using a frequency comparison circuit.

Operation The present invention uses the above-described configuration to compare the frequencies of the basic clock of the input reproduced signal and the extracted clock, control the frequency of the extracted clock, perform frequency pull-in, and then shift to phase lock. This realizes stable phase pull-in.

Embodiment A PLL circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the invention. 1 is a phase comparator, 2 is a filter, 3 is a VCo, 4 is a frequency comparator, 6
is a changeover switch.

The operation of the PLL circuit configured as described above will be explained.

The reproduced signal is input to a phase comparator 1 and a frequency comparator 4. The extraction error generated by VCO3 is similarly input to phase comparator 1 and frequency comparator 4. If phase lock is not applied here, the phase comparator output will appear in a random manner. Further, the frequency comparator output compares the frequencies of the input reproduction signal and the extracted clock, and detects whether the extracted clock is higher or lower than the reproduced signal. If the selector switch 6 is now switched to the frequency comparator 4, the frequency pull-in loop is closed. As a result, the frequency of the extracted clock generated by VCO3 matches that of the reproduced signal. After this, if the changeover switch is switched to the phase comparison side, since the frequencies match, it is possible to stably enter the phase lock state.

As described above, according to this embodiment, by providing the frequency comparator and the changeover switch, it is possible to achieve a more stable phase lock state.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the PLL circuit of the present invention.

1 is a phase comparator, 2 is a filter, 3 is a VCO, 4 is a frequency comparator, and 6 is an adder.

Here, if phase lock is not performed, the phase comparator 1 outputs acceleration and deceleration alternately.

Therefore, this integral value is zero. Furthermore, if the -shift phase lock state is entered, the frequencies will completely match, so the output of the frequency comparator 4 will also be 0.

Therefore, even if the changeover switch 6 shown in the first embodiment is replaced with a simple adder 6, the same effect can be obtained.

The above is the second embodiment of the present invention.

Effects of the Invention As described above, by providing a frequency pull-in loop using a frequency comparison circuit in a PLL circuit, stable pull-in to phase locking can be realized in any case.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PLL circuit in a first embodiment of the present invention, and FIG. 2 is a block diagram of a PLL circuit in a second embodiment of the present invention.
The block diagram of the L circuit, Figure 3, shows 1... phase comparator, 2... filter, 3... vCo,
4...Frequency comparator, 5...Switching switch, 6...Adder, 7...Disc, 8...Binoqua lp , 9... Preamplifier, 10... PLL circuit, 11...
- Motor control circuit, 12...Motor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4

Claims (2)

[Claims] (1) A phase comparator, a filter, a voltage controlled oscillator,
A PLL circuit characterized by consisting of a frequency comparator and a changeover switch. (2) The PLL circuit according to claim 1, wherein the changeover switch is an adder.