JPS6248917B2 - - Google Patents

Info

Publication number
JPS6248917B2
JPS6248917B2 JP3757281A JP3757281A JPS6248917B2 JP S6248917 B2 JPS6248917 B2 JP S6248917B2 JP 3757281 A JP3757281 A JP 3757281A JP 3757281 A JP3757281 A JP 3757281A JP S6248917 B2 JPS6248917 B2 JP S6248917B2
Authority
JP
Japan
Prior art keywords
semiconductor
layer
forming
layers
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3757281A
Other languages
Japanese (ja)
Other versions
JPS57152183A (en
Inventor
Ikuo Mito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3757281A priority Critical patent/JPS57152183A/en
Publication of JPS57152183A publication Critical patent/JPS57152183A/en
Publication of JPS6248917B2 publication Critical patent/JPS6248917B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/40Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/4025Array arrangements, e.g. constituted by discrete laser diodes or laser bar
    • H01S5/4031Edge-emitting structures
    • H01S5/4043Edge-emitting structures with vertically stacked active layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Description

【発明の詳細な説明】 本発明は同一基板上に発光波長の異なる複数の
埋め込みヘテロ構造半導体レーザを集積化した多
波長集積化半導体発光装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multi-wavelength integrated semiconductor light emitting device in which a plurality of buried heterostructure semiconductor lasers having different emission wavelengths are integrated on the same substrate.

最近、シリカガラス系光フアイバのOH含有量
が低減され波長1.25μm,1.40μm帯のOH吸収
損失ピークが見られなくなり、波長1.1μmから
1.6μmの広帯域に亘り伝送損失0.5dB/Kmとい
う低損失光フアイバが得られる様になつた。これ
に伴い、伝送可能波長領域を有効に利用し長距
離、大容量の伝送システムを構成できる光フアイ
バ波長分割多重伝送システムの重要性が増々大き
くなつて来た。光フアイバ波長分割多重伝送シス
テム用光源として、発光波長の異なる複数の半導
体レーザを同一基板上に構成した多波長集積化半
導体発光装置は光源形状の小形化、低価格化、性
能の安定性、信頼性の向上といつた利点を有して
おり、波長分割多重伝送システムの一層の高性能
化を図る上で有用な素子である。本願の発明者は
特願昭55−61671に記載し、出願したように多波
長集積化半導体発光装置を発明した。この多波長
集積化半導体発光装置は、第1図に示す様に、禁
制帯の異なる複数のInGaAsP層3−1〜3−3
を活性層とし、波長1.1μmから1.6μmまで任意
の波長の複数個の半導体レーザを集積できるこ
と、半導体レーザの構造は埋め込みヘテロ構造で
あり、低発振電流閾値での室温CW発振、等方的
な出射ビーム、安定な単一基本横モード発振等の
特性を有すること等の特徴を有している。しかし
ながら、第1図に示す多波長集積化半導体発光装
置の製造工程はInP基板1に、活性層となる複数
のInGaAsP層3−1〜3−3を含む多層膜を形
成する第1回目の液相エピタキシヤル成長(以下
LPEという)工程と、次にメサエツチングを施し
た後、電流閉じ込め層を形成する第2のLPE工程
と、全体を埋め込む第3のLPE工程との合計3回
のLPE工程を必要とし、全体の製造工程が長く、
必要工数が多くなるという欠点があつた。
Recently, the OH content of silica glass optical fiber has been reduced, and the OH absorption loss peak in the wavelength band of 1.25 μm and 1.40 μm is no longer observed, and from the wavelength of 1.1 μm
It has become possible to obtain a low-loss optical fiber with a transmission loss of 0.5 dB/Km over a wide band of 1.6 μm. Along with this, the importance of optical fiber wavelength division multiplexing transmission systems, which can construct long-distance, large-capacity transmission systems by effectively utilizing the transmittable wavelength range, has become increasingly important. As a light source for an optical fiber wavelength division multiplexing transmission system, a multi-wavelength integrated semiconductor light emitting device, in which multiple semiconductor lasers with different emission wavelengths are configured on the same substrate, has a compact light source shape, low cost, stable performance, and reliability. It has advantages such as improved performance, and is a useful element for further improving the performance of wavelength division multiplexing transmission systems. The inventor of the present application has invented a multi-wavelength integrated semiconductor light emitting device as described in Japanese Patent Application No. 55-61671 and filed. As shown in FIG. 1, this multi-wavelength integrated semiconductor light emitting device includes a plurality of InGaAsP layers 3-1 to 3-3 with different forbidden bands.
is used as the active layer, and multiple semiconductor lasers with arbitrary wavelengths from 1.1 μm to 1.6 μm can be integrated.The structure of the semiconductor laser is a buried heterostructure, which allows room temperature CW oscillation at a low oscillation current threshold, and isotropic It has characteristics such as an output beam and stable single fundamental transverse mode oscillation. However, the manufacturing process of the multi-wavelength integrated semiconductor light emitting device shown in FIG. phase epitaxial growth (hereinafter referred to as
A total of three LPE processes are required: a second LPE process to form a current confinement layer after mesa etching, and a third LPE process to embed the entire structure. The process is long,
The disadvantage was that it required more man-hours.

本発明は上記欠点を除き、液相エピタキシヤル
工程の数を減らし、全体の製造工程を短かくした
多波長集積化半導体発光装置の製造方法を提供す
るものである。
The present invention provides a method for manufacturing a multi-wavelength integrated semiconductor light emitting device that eliminates the above drawbacks, reduces the number of liquid phase epitaxial steps, and shortens the overall manufacturing process.

本発明の多波長集積化半導体発光装置の製造方
法は、半導体基板上に禁制帯幅が互に異なり互い
に接してはいない少くとも2層の活性層を含む複
数の半導体層をエピタキシヤル成長させて半導体
積層体を形成する第1のエピタキシヤル成長工程
と、前記半導体積層体を前記少くとも2層の活性
層のうちのそれぞれ一つの活性層の上面の少くと
も近傍付近までは個々に除去できるように一方向
に順次互いに異なつた深さでエツチングして段の
ついた半導体積層体を形成するエツチング工程
と、前記段の付いた半導体積層体の各段の表面上
に前記一方向に垂直な方向にストライプマスクを
形成する工程と前記ストライプマスクの形成され
ていない表面部分から前記少なくとも2層の活性
層の前記表面部分に対応する部分がおのおの除去
されるまでエツチングして少くとも2つの帯状メ
サ構造を形成するメサエツチング工程と、前記ス
トライプマスクを除去した後に前記少くとも2つ
の帯状メサストライプの上面のみを除いて前記半
導体基板と反対導電形の半導体層及び前記半導体
基板と同一導電形の半導体層を連続して積層した
後前記半導体基板と反対導電形の半導体層を全面
に亘つて繋がつて積層させる第2のエピタキシヤ
ル成長工程とを含んで構成される。
The method for manufacturing a multi-wavelength integrated semiconductor light emitting device of the present invention includes epitaxially growing a plurality of semiconductor layers including at least two active layers having mutually different forbidden band widths and not in contact with each other on a semiconductor substrate. a first epitaxial growth step for forming a semiconductor stack; an etching step of forming a stepped semiconductor stack by sequentially etching at different depths in one direction, and etching a layer in a direction perpendicular to the one direction on the surface of each step of the stepped semiconductor stack; forming a stripe mask on the substrate and etching the surface portion of the at least two active layers from the surface portion where the stripe mask is not formed until portions corresponding to the surface portions of the at least two active layers are respectively removed to form at least two band-like mesa structures; a mesa etching step to form a semiconductor layer of the opposite conductivity type to the semiconductor substrate and a semiconductor layer of the same conductivity type as the semiconductor substrate except for the upper surfaces of the at least two band-shaped mesa stripes after removing the stripe mask. The method includes a second epitaxial growth step in which, after successive lamination, semiconductor layers of the opposite conductivity type to the semiconductor substrate are connected and laminated over the entire surface.

本発明の多波長集積化半導体発光装置の製造方
法は、前記段の付いた半導体積層体を形成するエ
ツチング工程と前記ストライプマスクを形成する
工程との間に、前記段の付いた表面部分に対応す
るそれぞれの活性層よりも少なくとも上の部分を
前記半導体基板と反対導電形に反転させる不純物
拡散工程を追加して構成することができる。
In the method for manufacturing a multi-wavelength integrated semiconductor light emitting device of the present invention, between the etching step of forming the stepped semiconductor laminate and the step of forming the stripe mask, the stepped surface portion is etched. The semiconductor substrate may be configured by adding an impurity diffusion step for inverting at least a portion above each active layer to a conductivity type opposite to that of the semiconductor substrate.

上記2つの多波長集積化半導体発光装置の製造
方法に於て、前記半導体基板に面方位(001)の
InP基板を用い、前記活性層にIn1-xGaxAsyP1-y
(0<x<1,0<y≦1)層を用い、前記一方
向が<110>方向とすることが好ましい。
In the above two methods of manufacturing multi-wavelength integrated semiconductor light emitting devices, the semiconductor substrate has a plane orientation (001).
Using an InP substrate, the active layer is In 1-x GaxAsyP 1-y
It is preferable that a layer (0<x<1, 0<y≦1) is used, and the one direction is the <110> direction.

本発明の基礎となる事項をまず説明し、次に本
発明の実施例について説明することにする。
The basics of the present invention will be explained first, and then embodiments of the present invention will be explained.

まず、本発明の基礎となる事項を、面方位が
(001)のInP基板上に形成した<110>方向に伸
びるメサストライプを液相エピタキシヤル成長法
を用いてInP層で埋込み積層形状を形成する場合
を例にとつて、第2図a〜cを用いて説明する。
First, the basics of the present invention will be explained by forming a mesa stripe extending in the <110> direction formed on an InP substrate with a plane orientation of (001) and filling it with an InP layer using a liquid phase epitaxial growth method to form a stacked layer shape. The case will be explained using FIGS. 2a to 2c as an example.

まず、第2図aに示すように、面方位(100)
のInP基板12の上にメサ上部幅約1.5μm、メサ
の深さ約2μmのメサストライプ13を形成す
る。
First, as shown in Figure 2a, the surface orientation (100)
A mesa stripe 13 having a mesa upper width of about 1.5 μm and a mesa depth of about 2 μm is formed on the InP substrate 12 .

次に、第2図bに示すように、InP多結晶のIn
溶液への溶かし込み温度を610℃、冷却速度0.7
℃/分で温度降下させ、600℃の温度から2相溶
液状態で、メサ基板上にInP層を積層させる。こ
の場合に成長層厚を比較的薄くすると、各々0.6
μm程度の膜厚のp形InP層14、n形InP層1
5の2層を積層させても、メサ上面部には積層し
ない。これは、メサ側面部でのInP層の成長が速
く基板に接触しているIn溶液中のP濃度がメサ側
面部周囲、特にメサ上面部で減少することによる
ものと考えられる。
Next, as shown in Figure 2b, InP polycrystalline In
Dissolution temperature into solution is 610℃, cooling rate is 0.7
The temperature is lowered at a rate of °C/min, and an InP layer is deposited on the mesa substrate in a two-phase solution state from a temperature of 600 °C. In this case, if the growth layer thickness is made relatively thin, each 0.6
P-type InP layer 14, n-type InP layer 1 with a film thickness of about μm
Even if two layers of No. 5 are laminated, they will not be laminated on the upper surface of the mesa. This is considered to be because the growth of the InP layer on the side surfaces of the mesa is rapid, and the P concentration in the In solution in contact with the substrate decreases around the side surfaces of the mesa, particularly on the top surface of the mesa.

第2図cに示すようにInP層の成長膜厚を厚く
すれば、メサ上面部にも次第に積層し全体はメサ
部以外の平坦部で3μm程度の膜厚のp形InP層
16でほぼ平坦に埋められる。第2図cに示す埋
め込み形状は、後述する様に、メサ部のみに電流
が集中して流れる構造になつており、1回の埋め
込みLPE工程で以つて埋め込みヘテロ構造の半導
体レーザを作製することができる都合の良い形状
である。本発明は、上記のメサ基板上へのLPE成
長で以つて形成される層形状を利用したものであ
る。
As shown in Fig. 2c, if the thickness of the InP layer is increased, it will gradually be deposited on the upper surface of the mesa, and the whole will be almost flat with the p-type InP layer 16 having a thickness of about 3 μm in the flat areas other than the mesa area. buried in As will be described later, the buried shape shown in Figure 2c has a structure in which current flows concentrated only in the mesa portion, and a buried heterostructure semiconductor laser can be fabricated in one buried LPE process. It has a convenient shape that allows for The present invention utilizes the layer shape formed by LPE growth on the mesa substrate described above.

次に、本発明の実施例について説明する。 Next, examples of the present invention will be described.

第3図a〜dは本発明の一実施例を説明するた
めの製造工程における斜視図である。
FIGS. 3a to 3d are perspective views of the manufacturing process for explaining one embodiment of the present invention.

まず、第1図aに示すように、(001)面方位を
有し、SnでドープしたInP基板1の上に第1回目
のLPE工程により、順次にn形InPバツフア層2
(Teドープ、厚さ約5μm)及びInGaAsP第1活
性層3−1(λ=1.2μm、ノンドープ、厚さ0.2
μm)、n形InP第1中間層4−1(Teドープ、
厚さ0.5μm)、InGaAsP第2活性層3−2(λ=
1.3μm、ノンドープ、厚さ0.2μm)、n形InP第
2中間層4−2(Teドープ、厚さ0.5μm)、
InGaAsP第3活性層3−3(λ=1.55μm、ノン
ドープ、厚さ0.2μm)を順次積層した多層膜ウ
エハを形成する。成長温度は630℃、冷却速度は
0.7℃/分である。各々のInGaAsP活性層とInP層
との格子整合は△a/a0.1%である。
First, as shown in FIG.
(Te doped, about 5 μm thick) and InGaAsP first active layer 3-1 (λ=1.2 μm, non-doped, 0.2 μm thick)
μm), n-type InP first intermediate layer 4-1 (Te doped,
thickness 0.5 μm), InGaAsP second active layer 3-2 (λ=
1.3 μm, non-doped, 0.2 μm thick), n-type InP second intermediate layer 4-2 (Te doped, 0.5 μm thick),
A multilayer film wafer is formed by sequentially laminating InGaAsP third active layer 3-3 (λ=1.55 μm, non-doped, thickness 0.2 μm). Growth temperature is 630℃, cooling rate is
0.7℃/min. The lattice matching between each InGaAsP active layer and InP layer is Δa/a0.1%.

次に、第3図bに示すように、多層膜ウエハを
フオトレジストのマスクを用いてInGaAsPの第
1から第3の活性層3−1,3−2,3−3の
各々が200μm間隔で、InGaAsP第1活性層3−
1、InGaAsP第2活性層3−2、InGaAsP第3
活性層3−3の繰り返して表面に露出するように
選択性のエツチング液でエピタキシヤル表面をエ
ツチングする。この時繰り返し方向に直交する方
位は<110>になる様に選ぶ。
Next, as shown in FIG. 3b, the multilayer film wafer is coated with a photoresist mask so that each of the first to third active layers 3-1, 3-2, and 3-3 of InGaAsP is separated at intervals of 200 μm. , InGaAsP first active layer 3-
1. InGaAsP second active layer 3-2, InGaAsP third
The epitaxial surface is etched with a selective etching solution to repeatedly expose the surface of active layer 3-3. At this time, the direction perpendicular to the repetition direction is selected to be <110>.

次に、第3図cに示すように、<110>に平行に
幅2〜3μmのフオトレジストのストライプ17
を表面に200μm間隔の繰り返して露出した
InGaAsPの第1から第3の活性層3−1,3−
2,3−3のほぼ中央に位置して形成した後、こ
れをマスクとしてBr−メチルアルコールを用い
て約2μmの深さでメサエツチングし、第1、第
2、第3のメサストライプ18−1,18−2,
18−3が繰り返して形成されたメサ基板を作成
する。
Next, as shown in FIG.
was repeatedly exposed on the surface at intervals of 200 μm.
InGaAsP first to third active layers 3-1, 3-
2 and 3-3, and then using this as a mask, mesa etching is performed to a depth of about 2 μm using Br-methyl alcohol to form first, second and third mesa stripes 18-1. ,18-2,
A mesa substrate in which 18-3 is repeatedly formed is created.

次に、第3図dに示すように、エツチングマス
クとして使用したフオトレジストを剥離した後に
第2回目のLPE工程を行う。このLPE工程は第2
図で示したLPE成長と同様の条件で行う。即ちp
形InP電流ブロツク層5(Znドープ、平坦部での
厚さ0.6μm)、及びn形InP電流閉じ込め層6
(Teドープ、平坦部での厚さ0.6μm)をメサス
トライプの上面に積層させずそれ以外の部分では
連続して積層させ、その後p形InP埋め込み層7
(Znドープ、平坦部での厚さ3μm)を全面に亘
つて連続して積層し、最後にn形InGaAsP電極
形成層8(Teドープ、厚さ0.5μm)を積層させ
多波長構造ウエハを作成し終える。
Next, as shown in FIG. 3d, after the photoresist used as an etching mask is peeled off, a second LPE process is performed. This LPE process is the second
It is performed under the same conditions as the LPE growth shown in the figure. That is, p
InP type current blocking layer 5 (Zn doped, thickness at flat part 0.6 μm) and n type InP current confinement layer 6
(Te-doped, 0.6 μm thick at the flat part) is not laminated on the top surface of the mesa stripe, but is laminated continuously on the other parts, and then the p-type InP buried layer 7
(Zn-doped, 3 μm thick at the flat part) is continuously laminated over the entire surface, and finally an n-type InGaAsP electrode forming layer 8 (Te-doped, 0.5 μm thick) is laminated to create a multi-wavelength structure wafer. finish.

以上の工程が本発明による第1の実施例である
が、LPE工程が2回と、従来の3回のLPE工程に
比べ減少していることがわかる。
The above steps are the first example according to the present invention, and it can be seen that the number of LPE steps is two, which is fewer than the conventional three LPE steps.

第4図は第1の実施例の製造方法を用いて製造
した多波長集積化半導体発光装置の斜視図であ
る。
FIG. 4 is a perspective view of a multi-wavelength integrated semiconductor light emitting device manufactured using the manufacturing method of the first embodiment.

第1の実施例の製造方法により得られた多波長
構造ウエハに通常の方法により、SiO2・CVD膜
10を選択拡散マスクとして10μmの幅でp形
InP埋め込み層7に達する深さの第1、第2、第
3の選択Zn拡散層9−1,9−2,9−3を形
成し、その後n側にはAu−Ge−Niオーミツク性
電極11a、p側には第1から第3のAu−Znオ
ーミツク性電極11−1,11−2,11−3を
切り離して形成し、(110)面がフアブリーペロー
(Fabry−Perot)共振器の共振器面となる様に劈
開して多波長集積化半導体発光装置を製造する。
第4図の紙面左側から発光波長が1.2μm、1.3μ
m,1.5μmの3個の埋め込みヘテロ構造半導体
レーザが同一基板上に形成された構造をしてお
り、p側電極が各々切り離されているため、それ
ぞれ独立に駆動することができる。発光波長1.3
μmのレーザを例にとると第2のp側電極11−
2を正、n側電極11aを負とするバイアス電圧
を加えるとInGaAsP第2活性層3−2の部分は
pn接合の順バイアスであり、発光再結合が生じ
る。InGaAsP第2活性層3−2の下にある
InGaAsP第1活性層3−1の部分にはpn接合が
形成されていないため発光再結合は生じない。ま
た、InGaAsP第2活性層3−2以外の部分は
pnpn接合であり、負性抵抗の特性を示しターン
オン電圧以下では電流が殆んど流れない。従つ
て、電流はInGaAsP第2活性層3−2に集中し
て流れる。また、InGaAsP第2活性層3−2は
禁制帯幅の大きなInP層で周囲をり囲まれている
ためキヤリアの漏洩も少なく、室温での発振電流
閾値は20mA程度の低い値が得られた。更にま
た、発振横モードは単一基本モード発振であり、
注入電流を閾値の5倍程度まで大きくしても横モ
ードの形は変形しない。電流ブロツク層5電流閉
じ込め層6は、高温でのInGaAsP第1活性層3
−1周辺のInPのpn接合を介して流れる洩れ電流
の増加を抑制しておりその結果100℃程度まで連
続発振が可能である。発光波長1.3μm、1.5μm
レーザも上記の発光波長1.2μmのレーザと同様
の特性を示す。
The multi-wavelength structured wafer obtained by the manufacturing method of the first embodiment is coated with p-type film with a width of 10 μm using the SiO 2 CVD film 10 as a selective diffusion mask.
First, second, and third selective Zn diffusion layers 9-1, 9-2, and 9-3 with a depth reaching the InP buried layer 7 are formed, and then an Au-Ge-Ni ohmic electrode is formed on the n side. 11a, on the p side, the first to third Au-Zn ohmic electrodes 11-1, 11-2, 11-3 are formed separately, and the (110) plane is a Fabry-Perot resonator. A multi-wavelength integrated semiconductor light emitting device is manufactured by cleaving it into a vessel surface.
From the left side of the paper in Figure 4, the emission wavelength is 1.2μm and 1.3μm.
It has a structure in which three buried heterostructure semiconductor lasers with a diameter of 1.5 μm and 1.5 μm are formed on the same substrate, and because the p-side electrodes are separated from each other, they can be driven independently. Emission wavelength 1.3
Taking a μm laser as an example, the second p-side electrode 11-
When a bias voltage is applied with 2 being positive and the n-side electrode 11a being negative, the portion of the InGaAsP second active layer 3-2 becomes
This is a forward bias of the pn junction, and radiative recombination occurs. Underneath the InGaAsP second active layer 3-2
Since no pn junction is formed in the InGaAsP first active layer 3-1, radiative recombination does not occur. In addition, the parts other than the InGaAsP second active layer 3-2 are
It is a pnpn junction, exhibiting negative resistance characteristics, and almost no current flows below the turn-on voltage. Therefore, the current flows concentratedly in the InGaAsP second active layer 3-2. Furthermore, since the InGaAsP second active layer 3-2 is surrounded by an InP layer with a large forbidden band width, there is little carrier leakage, and a low oscillation current threshold of about 20 mA at room temperature was obtained. Furthermore, the oscillation transverse mode is a single fundamental mode oscillation,
Even if the injection current is increased to about five times the threshold value, the shape of the transverse mode does not change. The current blocking layer 5 and the current confinement layer 6 are formed by forming the InGaAsP first active layer 3 at high temperature.
The increase in leakage current flowing through the InP pn junction around -1 is suppressed, and as a result, continuous oscillation is possible up to about 100°C. Emission wavelength 1.3μm, 1.5μm
The laser also exhibits characteristics similar to the above-mentioned laser with an emission wavelength of 1.2 μm.

第5図a〜eは本発明の第2の実施例を説明す
るための主な製造工程における断面図である。
FIGS. 5a to 5e are cross-sectional views showing main manufacturing steps for explaining the second embodiment of the present invention.

第1の実施例と異なる点は、第1回目のLPE工
程で形成したInGaAsP活性層を表面に露出させ
ないことである。
The difference from the first example is that the InGaAsP active layer formed in the first LPE process is not exposed to the surface.

第5図aに示すように、第1の実施例の多層膜
ウエハに付け加えn形InP第3中間層4−3(Te
ドープ、厚さ0.5μm)を第1回目のLPE工程で
積層させ、InGaAsP活性層を露出させないよう
に覆う。
As shown in FIG. 5a, an n-type InP third intermediate layer 4-3 (Te
A doped layer (0.5 μm thick) is deposited in the first LPE process to cover the InGaAsP active layer so as not to expose it.

次に、第5図bに示すように、この多層膜ウエ
ハにフオトレジストをマスクとして、200μmお
きに、n形InP第1中間層4−1、n形InP第2
中間層4−2、n形InP第3中間層4−3が繰り
返して露出するように選択性のエツチング液を用
いてエピタキシヤル表面をエツチングする。繰り
返しの方位は第1の実施例の場合と同じである。
Next, as shown in FIG. 5b, using a photoresist as a mask on this multilayer film wafer, the n-type InP first intermediate layer 4-1, the n-type InP second intermediate layer 4-1, and the n-type InP second
The epitaxial surface is etched using a selective etching solution so that the intermediate layer 4-2 and the n-type InP third intermediate layer 4-3 are repeatedly exposed. The orientation of the repetition is the same as in the first embodiment.

次に、第5図cに示すように、表面から露出し
たn形InPの第1から第3の中間層4−1,4−
2,4−3の導電形をp形InPの第1、第2、第
3クラツド層19−1,19−2,19−3へと
反転する。
Next, as shown in FIG. 5c, the first to third intermediate layers 4-1, 4- of n-type InP exposed from the surface are
The conductivity types of layers 2 and 4-3 are inverted to first, second and third cladding layers 19-1, 19-2 and 19-3 of p-type InP.

次に、第5図dに示すように、メサエツチング
を施し、メサ基板を形成する。
Next, as shown in FIG. 5d, mesa etching is performed to form a mesa substrate.

次に、第5図eに示すように、第2回目のLPE
工程を行つてメサ基板をInP層で埋め込み、多波
長構造ウエハを形成する。
Next, as shown in Figure 5e, the second LPE
A process is performed to fill the mesa substrate with an InP layer and form a multi-wavelength structured wafer.

以上の工程は、第1の実施例の場合と似通つて
いるがInGaAsP活性層を表面に露出させないこ
とにより、製造工程中にInGaAsP活性層に機械
的損傷もしくは熱的な損傷を与える危険性が第1
の実施例の場合に比較して少なくなつている。
The above steps are similar to those in the first embodiment, but by not exposing the InGaAsP active layer to the surface, there is a risk of mechanical or thermal damage to the InGaAsP active layer during the manufacturing process. 1st
This is smaller than in the case of the embodiment.

第6図は第2の実施例の製造方法を用いて製造
した多波長集積化半導体発光装置の斜視図であ
る。
FIG. 6 is a perspective view of a multi-wavelength integrated semiconductor light emitting device manufactured using the manufacturing method of the second embodiment.

第1の実施例の場合の多波長集積化半導体発光
装置と異なる点はInGaAsPの第1から第3の活
性層3−1,3−2,3−3の上に0.5μmの厚
さのp形InPの第1から第3のクラツド層19−
1,19−2,19−3が挿入された点であるが
各個別の半導体レーザの特性は第1の実施例の場
合と同様であり、発振電流閾値は20mA程度で、
又単一基横モード発振を示した。
The difference from the multi-wavelength integrated semiconductor light emitting device in the first embodiment is that a 0.5 μm thick layer is formed on the first to third active layers 3-1, 3-2, and 3-3 of InGaAsP. InP type first to third cladding layers 19-
1, 19-2, and 19-3 are inserted, but the characteristics of each individual semiconductor laser are the same as in the first embodiment, and the oscillation current threshold is about 20 mA.
It also showed single-base transverse mode oscillation.

本発明は上記の基本的な2つの実施例の他にい
くつかの変形が可能である。まず、発光波長は
1.2μm,1.3μm,1.5μmのみに限定されること
はなく他の波長でも良い。次、InGaAsP活性層
は発光波長が1.2μm,1.3μm,1.5μmの順序で
積層されているがこの順序に限定されるものでは
ない。n形InP電流閉じ込め層6は電流を
InGaAsP活性層に集中させる機能を有していれ
ば良いので、n形のInGaAsP層または半絶縁性
のInP層もしくはInGaAsP層であつても構わな
い。また、材料はInGaAsP系に限らず、GaAlAs
系、等の化合物半導体でも構わない。
The present invention can be modified in several ways in addition to the two basic embodiments described above. First, the emission wavelength is
The wavelength is not limited to 1.2 μm, 1.3 μm, and 1.5 μm, and other wavelengths may be used. Next, the InGaAsP active layers are stacked in the order of emission wavelengths of 1.2 μm, 1.3 μm, and 1.5 μm, but the order is not limited to this. The n-type InP current confinement layer 6 allows the current to
It may be an n-type InGaAsP layer or a semi-insulating InP layer or InGaAsP layer, as long as it has the function of concentrating on the InGaAsP active layer. In addition, the material is not limited to InGaAsP, but also GaAlAs
It may be a compound semiconductor such as a type of semiconductor.

以上詳細に説明しように、本発明によれば、従
来よりも液相エピタキシヤル成長工程数を減少さ
せ、低発振電流閾値、単一基本横モード発振など
の優れた特性を有する多波長集積化半導体発光装
置の製造方法が得られるのでその効果は大きい。
As explained in detail above, according to the present invention, the number of liquid phase epitaxial growth steps is reduced compared to the conventional method, and a multi-wavelength integrated semiconductor having excellent characteristics such as a low oscillation current threshold and single fundamental transverse mode oscillation is produced. The effect is great because a method for manufacturing a light emitting device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の多波長集積化半導体発光装置の
一例の斜視図、第2図a〜cは本発明の基礎とな
る事項を説明するための斜視図、第3図a〜dは
本発明の第1の実施例を説明するための製造工程
における斜視図、第4図は第1の実施例を用いて
製造した多波長集積化半導体発光装置の斜視図、
第5図a〜eは本発明の第2の実施例を説明する
ための製造工程における斜視図、第6図は第2の
実施例を用いて製造した多波長集積化半導体発光
装置の斜視図である。 1……n形InP基板、2……n形InPバツフア
層、3−1……発光波長1.2μmのInGaAsP第1
活性層、3−2……発光波長1.3μmのInGaAsP
第2活性層、3−3……発光波長1.5μmのInG−
aAsP第3活性層、4−1……n形InP第1中間
層、4−2……n形InP第2中間層、4−3……
n形InP第3中間層、5……p形InP電流ブロツ
ク層、6……n形InP電流閉じ込め層、7……p
形InP埋め込み層、8……n形InGaAsP電極形成
層、9−1,9−2,9−3……Zn拡散領域、
10……SiO2CVD膜、11−1,11−2,1
1−3……Au−Znオーミツク性電極、11a…
…Au−Ge−Niオーミツク性電極、12……n形
InP基板、13……InPメサストライプ、14…
…p形InP層、15……n形InP層、16……p
形InP層、17……フオトレジストのストライプ
膜、18−1,18−2,18−3……活性層を
含むメサストライプ19−1,19−2,19−
3……p形InP第1、第2、第3クラツド層。
FIG. 1 is a perspective view of an example of a conventional multi-wavelength integrated semiconductor light emitting device, FIGS. 2 a to c are perspective views for explaining the basics of the present invention, and FIGS. FIG. 4 is a perspective view of a multi-wavelength integrated semiconductor light emitting device manufactured using the first example;
5a to 5e are perspective views of the manufacturing process for explaining the second embodiment of the present invention, and FIG. 6 is a perspective view of a multi-wavelength integrated semiconductor light emitting device manufactured using the second embodiment. It is. 1... n-type InP substrate, 2... n-type InP buffer layer, 3-1... InGaAsP first layer with emission wavelength of 1.2 μm
Active layer, 3-2... InGaAsP with emission wavelength of 1.3 μm
Second active layer, 3-3... InG- with emission wavelength of 1.5 μm
aAsP third active layer, 4-1... n-type InP first intermediate layer, 4-2... n-type InP second intermediate layer, 4-3...
n-type InP third intermediate layer, 5...p-type InP current blocking layer, 6...n-type InP current confinement layer, 7...p
InP type buried layer, 8... n-type InGaAsP electrode forming layer, 9-1, 9-2, 9-3... Zn diffusion region,
10...SiO 2 CVD film, 11-1, 11-2, 1
1-3...Au-Zn ohmic electrode, 11a...
...Au-Ge-Ni ohmic electrode, 12...n type
InP substrate, 13... InP mesa stripe, 14...
...p-type InP layer, 15...n-type InP layer, 16...p
type InP layer, 17...photoresist stripe film, 18-1, 18-2, 18-3... mesa stripe including active layer 19-1, 19-2, 19-
3...p-type InP first, second, and third cladding layers.

Claims (1)

【特許請求の範囲】 1 半導体基板上に、禁制帯幅が互いに異なり互
いに接してはいない少くとも2層の活性層を含む
複数の半導体層をエピタキシヤル成長させて半導
体積層体を形成する第1のエピタキシヤル成長工
程と、前記半導体積層体を、前記少くとも2層の
活性層のうちのそれぞれ一つの活性層の上面の少
くとも近傍付近までは個々に除去できるように一
方向に順次互いに異なつた深さでエツチングして
段のついた半導体積層体を形成するエツチング工
程と、前記段の付いた半導体積層体の各段の表面
上に前記一方に垂直な方向にストライプマスクを
形成する工程と、前記ストライプマスクの形成さ
れた段付き半導体積層体を前記ストライプマスク
の形成されていない表面部分から前記少なくとも
2層の活性層の前記表面部分に対応する部分がお
のおの除去されるまでエツチングして少くとも2
つの帯状メサ構造を形成するメサエツチング工程
と、前記ストライプマスクを除去した後に前記少
くとも2つの帯状メサストライプの上面のみを除
いて前記半導体基板と反対導電形の半導体層及び
前記半導体基板と同一導電形の半導体層を連続し
て積層した後前記半導体基板と反対導電形の半導
体層を全面に亘つて繋がつて積層させる第2のエ
ピタキシヤル成長工程とを含むことを特徴とする
多波長集積化半導体発光装置の製造方法。 2 半導体基板上に、禁制帯幅が互いに異なり互
いに接してはいない少くとも2層の活性層を含む
複数の半導体層をエピタキシヤル成長させて半導
体積層体を形成する第1のエピタキシヤル成長工
程と、前記半導体積層体を、前記少くとも2層の
活性層のうちのそれぞれ一つの活性層の上面の少
くとも近傍付近までは個々に除去できるように一
方向に順次互いに異なつた深さでエツチングして
段のついた半導体積層体を形成するエツチング工
程と、前記段の付いた表面部分に対応するそれぞ
れの活性層よりも少なくとも上の部分を前記半導
体基板と反対導電形に反転させる不純物拡散工程
と、前記段の付いた半導体積層体の各段の表面上
に前記一方向に垂直な方向にストライプマスクを
形成する工程と、前記ストライプマスクの形成さ
れた段付き半導体積層体を前記ストライプマスク
の形成されていない表面部分から前記少なくとも
2層の活性層の前記表面部分に対応する部分がお
のおの除去されるまでエツチングして少くとも2
つの帯状メサ構造を形成するメサエツチング工程
と、前記ストライプマスクを除去した後に前記少
くとも2つの帯状メサストライプの上面のみを除
いて前記半導体基板と反対導電形の半導体層及び
前記半導体基板と同一導電形の半導体層を連続し
て積層した後前記半導体基板と反対導電形の半導
体層を全面に亘つて繋がつて積層させる第2のエ
ピタキシヤル成長工程とを含むことを特徴とする
多波長集積化半導体発光装置の製造方法。 3 前記半導体基板が面方位(001)のInP基板
であり、前記活性層がIn1-xGaxAsyP1-y(0<x
<1,0<y≦1)層であり、前記一方向が<1
10>方向であることを特徴とする特許請求の範
囲第1項記載の多波長集積化半導体発光装置の製
造方法。 4 前記半導体基板が面方位(001)のInP基板
であり、前記活性層がIn1-XGaxAsyP1-Y(0<x
<1,0<y≦1)層であり、前記一方向が<1
10>方向であることを特徴とする特許請求の範
囲第2項記載の多波長集積化半導体発光装置の製
造方法。
[Claims] 1. A first method of forming a semiconductor stack by epitaxially growing a plurality of semiconductor layers including at least two active layers having different forbidden band widths and not in contact with each other on a semiconductor substrate. an epitaxial growth step, and the semiconductor stack is sequentially grown in different directions in one direction so that at least the vicinity of the upper surface of each of the at least two active layers can be individually removed. an etching step of forming a stepped semiconductor stack by etching to a depth of 100 nm, and a step of forming a stripe mask in a direction perpendicular to the one on the surface of each step of the stepped semiconductor stack; , etching the stepped semiconductor laminate on which the stripe mask is formed from the surface portion where the stripe mask is not formed until portions corresponding to the surface portions of the at least two active layers are respectively removed; Tomo 2
a mesa etching step for forming two strip-shaped mesa structures, and after removing the stripe mask, a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate and a semiconductor layer having the same conductivity type as the semiconductor substrate except for the upper surface of the at least two strip-shaped mesa stripes. A multi-wavelength integrated semiconductor light emitting device comprising: successively stacking semiconductor layers, and then a second epitaxial growth step of connecting and stacking semiconductor layers of the opposite conductivity type to the semiconductor substrate over the entire surface. Method of manufacturing the device. 2. A first epitaxial growth step of forming a semiconductor stack by epitaxially growing a plurality of semiconductor layers including at least two active layers having different forbidden band widths and not in contact with each other on a semiconductor substrate; , etching the semiconductor stack in one direction at different depths so that at least the vicinity of the upper surface of each of the at least two active layers can be individually removed; an etching step for forming a stepped semiconductor stack; and an impurity diffusion step for inverting at least a portion above each active layer corresponding to the stepped surface portion to a conductivity type opposite to that of the semiconductor substrate. , forming a stripe mask in a direction perpendicular to the one direction on the surface of each step of the stepped semiconductor stack; forming a stripe mask on the stepped semiconductor stack on which the stripe mask is formed; At least two etching steps are performed by etching at least two active layers from the unetched surface portions until respective portions of the at least two active layers corresponding to the surface portions are removed.
a mesa etching step for forming two strip-shaped mesa structures, and after removing the stripe mask, a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate and a semiconductor layer having the same conductivity type as the semiconductor substrate except for the upper surface of the at least two strip-shaped mesa stripes. A multi-wavelength integrated semiconductor light emitting device comprising: successively stacking semiconductor layers, and then a second epitaxial growth step of connecting and stacking semiconductor layers of the opposite conductivity type to the semiconductor substrate over the entire surface. Method of manufacturing the device. 3. The semiconductor substrate is an InP substrate with plane orientation (001), and the active layer is In 1-x Ga x As y P 1-y (0<x
<1,0<y≦1) layer, and the one direction is <1
10. The method of manufacturing a multi-wavelength integrated semiconductor light emitting device according to claim 1, wherein the direction is 10>. 4. The semiconductor substrate is an InP substrate with plane orientation (001), and the active layer is In 1-X Ga x As y P 1-Y (0<x
<1,0<y≦1) layer, and the one direction is <1
3. The method of manufacturing a multi-wavelength integrated semiconductor light emitting device according to claim 2, wherein the direction is 10>.
JP3757281A 1981-03-16 1981-03-16 Manufacture of multiple wave length integrated semiconductor light emitting device Granted JPS57152183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3757281A JPS57152183A (en) 1981-03-16 1981-03-16 Manufacture of multiple wave length integrated semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3757281A JPS57152183A (en) 1981-03-16 1981-03-16 Manufacture of multiple wave length integrated semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JPS57152183A JPS57152183A (en) 1982-09-20
JPS6248917B2 true JPS6248917B2 (en) 1987-10-16

Family

ID=12501238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3757281A Granted JPS57152183A (en) 1981-03-16 1981-03-16 Manufacture of multiple wave length integrated semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPS57152183A (en)

Also Published As

Publication number Publication date
JPS57152183A (en) 1982-09-20

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