JPS6250077B2 - - Google Patents
Info
- Publication number
- JPS6250077B2 JPS6250077B2 JP11686783A JP11686783A JPS6250077B2 JP S6250077 B2 JPS6250077 B2 JP S6250077B2 JP 11686783 A JP11686783 A JP 11686783A JP 11686783 A JP11686783 A JP 11686783A JP S6250077 B2 JPS6250077 B2 JP S6250077B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- ceramic
- manufacturing
- substrate
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000919 ceramic Substances 0.000 claims description 39
- 239000010409 thin film Substances 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 10
- 238000010304 firing Methods 0.000 claims description 8
- 239000011148 porous material Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000000843 powder Substances 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 5
- 230000003746 surface roughness Effects 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 4
- 238000007606 doctor blade method Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000009834 vaporization Methods 0.000 description 2
- 230000008016 vaporization Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000001856 Ethyl cellulose Substances 0.000 description 1
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 1
- -1 Mo and W Chemical class 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920001249 ethyl cellulose Polymers 0.000 description 1
- 235000019325 ethyl cellulose Nutrition 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明は薄膜用セラミツク回路基板の製造法に
関するものであり、さらに詳しくは薄膜加工によ
る導体の断線がほとんどない薄膜用セラミツク回
路基板の製造法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thin film ceramic circuit board, and more particularly to a method for manufacturing a thin film ceramic circuit board in which there is almost no disconnection of conductors during thin film processing.
従来、高密度配線基板に用いられる薄膜用セラ
ミツク回路基板の製造法としては、第１図のフロ
ーシートに示すように、アルミナ、ベリリア等の
セラミツクグリーンシートをドクターブレード法
等により成形し、所定寸法に切断およびスルーホ
ール孔を穿設し、その表面およびスルーホールに
MoあるいはＷ等の高融点金属よりなるメタライ
ズペーストを用いて所要のパターンを印刷し、そ
の表面にセラミツクグリーンシート又は絶縁ペー
ストとメタライズペーストとを複数回交互に多層
化した後乾燥し、還元性雰囲気中で焼成してセラ
ミツクスを一体化すると同時に該セラミツクス中
に導体金属層の所要パターンを形成し、好ましく
は露出パターンの表面にNiメツキを施す方法が
広く知られている。 Conventionally, as shown in the flow sheet of Fig. 1, the manufacturing method for thin-film ceramic circuit boards used for high-density wiring boards is to form ceramic green sheets of alumina, beryllia, etc. by a doctor blade method, etc., and to form them into predetermined dimensions. Cut and drill through-hole holes in the surface and through-holes.
A desired pattern is printed using a metallization paste made of a high-melting point metal such as Mo or W, and ceramic green sheets or insulating paste and metallization paste are alternately layered several times on the surface, then dried and dried in a reducing atmosphere. A widely known method is to integrate the ceramics by firing in the ceramics, simultaneously form a required pattern of a conductive metal layer in the ceramics, and preferably apply Ni plating to the surface of the exposed pattern.
しかしながら、このような製造法によつてつく
られる基板上に例えば高密度配線をするために
Al等を蒸着、スパツタリング等により薄膜加工
で被覆する場合、薄膜加工の導体がしばしば断線
することがあつた。 However, in order to perform high-density wiring on a substrate made by this manufacturing method, for example,
When coating Al or the like with a thin film process such as vapor deposition or sputtering, the thin film process conductor often breaks.
これはセラミツクグリーンシートを複数層形成
し、焼成によつて一体的に結合する前記のような
セラミツクパツケージの製造法では、製法および
製造法の制約による原料純度並びに加工時に表面
欠陥をつくることにより基板の表面粗さが荒く、
しかも焼成後の基板中に２〜４％の気化の存在は
避けられず、かつ焼成後の基板表面にも50〜100
μｍ程度の開気孔がしばしば残留することがあ
る。そして、このような開気孔が残留する基板上
に数μｍ程度の薄膜加工を施しても、導体回路が
完全につながらず、断線する欠点があつた。 This is due to the manufacturing method of ceramic packages as described above, in which multiple layers of ceramic green sheets are formed and bonded together by firing, but due to constraints on the raw material purity and the production process, surface defects may be created on the substrate. The surface roughness of
Moreover, the presence of 2-4% vaporization in the substrate after firing is unavoidable, and the presence of 50-100% vaporization on the substrate surface after firing is unavoidable.
Open pores on the order of μm often remain. Even if a thin film of several micrometers is processed on a substrate in which such open pores remain, the conductor circuits are not completely connected, resulting in disconnection.
本発明の目的は、薄膜加工形成面に開気孔が存
在しないセラミツクス内部に回路形成された表面
平滑な薄膜用セラミツク回路基板の製造法を提供
するものであり、さらに他の目的は、薄膜加工導
体の断線の心配がほとんどない薄膜用セラミツク
回路基板の製造法を提供するにある。 An object of the present invention is to provide a method for manufacturing a ceramic circuit board for thin film, which has a smooth surface and has a circuit formed inside the ceramic without open pores on the thin film processing surface. To provide a method for manufacturing a thin film ceramic circuit board in which there is almost no fear of wire breakage.
本発明は未焼成絶縁層と高融点金属よりなる導
電層とを交互に多層化した後焼成してセラミツク
ス内に導体よりなるパターン回路を形成した基板
をつくり、その基板の少なくとも薄膜回路形成面
を研磨し、後表面に露出した開気孔部にセラミツ
ク粉末を充填して再焼成することを特徴とする薄
膜用セラミツクパツケージの製造法である。 The present invention produces a substrate in which a patterned circuit made of a conductor is formed in ceramics by alternately laminating unfired insulating layers and conductive layers made of a high-melting point metal and then firing the ceramic, and at least the thin film circuit forming surface of the substrate is made. This is a method for manufacturing a ceramic package for thin film, which is characterized by polishing, filling ceramic powder into the open pores exposed on the rear surface, and re-firing.
本発明の更に詳しい構成を具体的なフローシー
トで示す第２図に基づいて説明すると、ベリリ
ア、アルミナ好ましくは純度84〜94重量％のアル
ミナより成るセラミツクグリーンシートをドクタ
ーブレード法によつて成形し、所定寸法に切断
後、スルーホール等の孔を穿設し、そのセラミツ
クグリーンシートの表面およびスルーホール中
に、Mo、Ｗ等の高融点金属およびフリツト粉
末、エチルセルロース、ブチラール樹脂、アクリ
ル樹脂等のバインダーを含む導電性ペーストを用
いて印刷法により所定のパターンを形成する。そ
して更にセラミツクグリーンシート又は好ましく
は同質の絶縁ペーストと導電性ペーストとを交互
に複数層多層化し、未焼成絶縁層と高融点金属よ
りなる導体層とを交互に積層した積層体をつく
り、後還元性雰囲気中で焼成してセラミツクスを
一体焼結するとともに該セラミツクス内に導体よ
りなるパターン回路を形成した基板を製作する。 The more detailed structure of the present invention will be explained based on FIG. 2 which shows a specific flow sheet. A ceramic green sheet made of beryllia, alumina, preferably alumina with a purity of 84 to 94% by weight is formed by a doctor blade method. After cutting to a predetermined size, holes such as through holes are drilled, and high melting point metals such as Mo and W, frit powder, ethyl cellulose, butyral resin, acrylic resin, etc. are applied to the surface of the ceramic green sheet and in the through holes. A predetermined pattern is formed by a printing method using a conductive paste containing a binder. Then, ceramic green sheets or preferably homogeneous insulating paste and conductive paste are alternately layered to create a laminate in which unfired insulating layers and conductor layers made of high melting point metal are alternately laminated, and post-reduction is performed. The ceramics are integrally sintered by firing in a neutral atmosphere, and a substrate is manufactured in which a patterned circuit made of a conductor is formed within the ceramics.
次いで、その基板の少なくとも薄膜回路形成面
を＃600〜＃2000の砥粒を用いてラツピングマシ
ンで研磨し、研磨面粗さをHRnax7μｍ以下とす
る。そして、研磨面に露出した開気孔中に基板と
同材質よりなるセラミツク粉末を充填する。この
開気孔中へのセラミツク粉末の充填は、セラミツ
ク微粉末に溶媒等を加えたものを用いるとよい。 Next, at least the surface on which the thin film circuit is formed of the substrate is polished with a lapping machine using abrasive grains of #600 to #2000, so that the roughness of the polished surface is HR nax 7 μm or less. Then, ceramic powder made of the same material as the substrate is filled into the open pores exposed on the polished surface. To fill the open pores with ceramic powder, it is preferable to use fine ceramic powder to which a solvent or the like is added.
そして、乾燥後、1250〜1500℃の温度で再焼成
することにより、表面粗さがHRnax5μｍ以下の
平滑な開気孔の全くない薄膜回路形成面を持つた
セラミツクパツケージが得られるものである。従
つて、薄膜回路形成面が均一平滑であるので、例
えば該面上に５μｍ程度の薄膜パターンを蒸着に
よつて形成しても、パターン断線の全くないもの
である。 After drying, the ceramic package is re-fired at a temperature of 1250 to 1500 DEG C. to obtain a ceramic package having a smooth thin film circuit forming surface with a surface roughness of HR nax 5 .mu.m or less and no open pores. Therefore, since the thin film circuit forming surface is uniformly smooth, even if a thin film pattern of about 5 μm is formed on the surface by vapor deposition, for example, there will be no pattern breakage.
なお、研磨面の表面粗さをHRnax7μｍ以下と
するのは、７μｍを越えるような表面の粗さで
は、薄膜加工による薄膜パターンの断線が避けら
れないためである。 The reason why the surface roughness of the polished surface is HR nax 7 μm or less is because if the surface roughness exceeds 7 μm, disconnection of the thin film pattern due to thin film processing cannot be avoided.
本発明には以下のような効果が得られる。 The present invention provides the following effects.
(1) 表面が極めて平滑な薄膜パターン形成面をも
つたセラミツク回路基板が得られる。(1) A ceramic circuit board with an extremely smooth surface on which a thin film pattern is formed can be obtained.
(2) 薄膜パターン導体の断線のないセラミツク回
路基板が得られる。(2) A ceramic circuit board without disconnection of the thin film pattern conductor can be obtained.
(3) セラミツクス基板内に多層回路を持つた高密
度回路基板ができる。(3) High-density circuit boards with multilayer circuits inside ceramic substrates can be created.
本発明は高密度配線基板として用いられる薄膜
用セラミツク回路基板の製造法として有用であ
る。 INDUSTRIAL APPLICATION This invention is useful as a manufacturing method of the thin film ceramic circuit board used as a high-density wiring board.
第１図は従来の薄膜用セラミツク回路基板の製
造工程を示すフローシートであり、第２図は本発
明の薄膜用セラミツク回路基板の製造工程を示す
フローシートである。
FIG. 1 is a flow sheet showing the manufacturing process of a conventional thin film ceramic circuit board, and FIG. 2 is a flow sheet showing the manufacturing process of the thin film ceramic circuit board of the present invention.
Claims (1)
とを交互に層状に多層化した後、焼成してセラミ
ツクス内に導体よりなる薄膜回路パターンを形成
し、該回路パターンと導通した導体を孔部を介し
て表面に露出した基板をつくり、その基板の少な
くとも薄膜回路パターン形成面を研磨し、後表面
に露出した開気孔部にセラミツク粉末を充填して
再焼成することを特徴とする薄膜用セラミツク回
路基板の製造法。 ２ 未焼成絶縁層が純度84〜94重量％のアルミナ
である特許請求の範囲第１項記載の薄膜用セラミ
ツクパツケージの製造法。 ３ 薄膜回路形成面をHRnax7μｍ以下に研磨す
る特許請求の範囲第１項又は第２項記載の薄膜用
セラミツクパツケージの製造法。 ４ 再焼成後の薄膜回路形成面の表面粗さが
HRnax5μｍ以下である特許請求の範囲第１項、
第２項又は第３項記載の薄膜用セラミツクパツケ
ージの製造法。[Scope of Claims] 1. A thin film circuit pattern made of a conductor is formed in ceramics by forming a multilayer structure in which unfired insulating layers and conductor layers made of a high-melting point metal are alternately formed and then fired. A method is to create a substrate in which a conductor electrically connected to the substrate is exposed on the surface through the hole, polish at least the surface on which the thin film circuit pattern is formed, and then fill the open pores exposed on the surface with ceramic powder and refire it. A method for manufacturing a thin film ceramic circuit board characterized by: 2. The method for producing a thin film ceramic package according to claim 1, wherein the unfired insulating layer is alumina with a purity of 84 to 94% by weight. 3. A method for manufacturing a thin film ceramic package according to claim 1 or 2, wherein the thin film circuit forming surface is polished to HR nax 7 μm or less. 4 The surface roughness of the thin film circuit forming surface after re-firing
Claim 1, wherein the HR nax is 5 μm or less;
A method for producing a thin film ceramic package according to item 2 or 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11686783A JPS6010696A (en) | 1983-06-30 | 1983-06-30 | Method of producing thin film ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11686783A JPS6010696A (en) | 1983-06-30 | 1983-06-30 | Method of producing thin film ceramic circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6010696A JPS6010696A (en) | 1985-01-19 |
| JPS6250077B2 true JPS6250077B2 (en) | 1987-10-22 |
Family
ID=14697591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11686783A Granted JPS6010696A (en) | 1983-06-30 | 1983-06-30 | Method of producing thin film ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010696A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6416287U (en) * | 1987-07-20 | 1989-01-26 | ||
| JPH0315490A (en) * | 1988-09-03 | 1991-01-23 | Wilkinson Sword Gmbh | Razor |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62216251A (en) * | 1986-03-17 | 1987-09-22 | Toshiba Corp | High thermal conductive substrate |
| JPH0770644B2 (en) * | 1986-03-27 | 1995-07-31 | 株式会社東芝 | Thermal conductive substrate |
| JP2727602B2 (en) * | 1988-11-07 | 1998-03-11 | 富士通株式会社 | Method for manufacturing multilayer circuit board |
| KR20120015948A (en) * | 2010-08-13 | 2012-02-22 | 삼성전기주식회사 | Manufacturing method of ceramic substrate and ceramic substrate using same |
| KR101153492B1 (en) * | 2010-08-24 | 2012-06-11 | 삼성전기주식회사 | Manufacturing method for ceramic substrate for probe card and ceramic substrate for probe card |
-
1983
- 1983-06-30 JP JP11686783A patent/JPS6010696A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6416287U (en) * | 1987-07-20 | 1989-01-26 | ||
| JPH0315490A (en) * | 1988-09-03 | 1991-01-23 | Wilkinson Sword Gmbh | Razor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6010696A (en) | 1985-01-19 |
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