JPS6250940A - Control system for main memory device - Google Patents

Abstract

PURPOSE:To shortena memory access time by dividing the response signal from a main memory device to CPU into two, estimating the time from the releasing of clock stoppage of the CPU to the occurrence of clock for fetching the data and sending, first, the first response signal. CONSTITUTION:A main memory device 12 starts the action by the address sent from a main memory control device 11 and a memory access requesting signal SRVi. The first response signal sending circuit 19 sends the first response signal SRVO1 to the second response signal sending circuit 20 and sends the second resonse signal SRVO2 prior to read data DATAxx to the device 11. The device 11 receives the signal SRVO 1, sends a response signal ANS to the CPU 10, the CPU 10 releases the clock by the signal ANS, executes the micro program and sets data DATAxx to the register. Thus, the data sent simultaneously with the signal SRVO2 can be instantaneously fetched and the memory access time can be shortened.

Description

[Detailed Description of the Invention] [Summary] A main memory that stops the clock of the central processing unit upon memory access from the central processing unit, cancels the clock stop with a response signal from the main storage side, and performs data processing. In the device control method, the response signal from the main storage device is
Divided into two signals: the first response signal for canceling clock stop and the second response signal generated at the same timing as before.

By canceling the cross-crossing stop based on the first response signal that is issued first, loss time from clock release to data capture clock generation is eliminated, and memory access by the central processing unit is sped up.

[Conventional technology and problems]

In general, access requests to main storage.

There are access requests from the central processing unit and direct memory access (DMA) requests from the channel devices.

The main memory operates on access request signals and access response signals. The central processing unit.

To speed up processing, the clock is stopped after a memory access request from the central processing unit until a response signal is received from the main memory side.

FIG. 3 shows a time chart according to the conventional method.

The central processing unit issues a read access request Read RE
When Q is issued, the main memory controller sets the bus to busy gcP.
As BsY, an access request signal 5RVi (service in signal) is sent to the main storage device. The main memory.

When the data is ready, a response signal 5RVO (service out signal) is sent together with the data DATAxx, and the main memory controller sends a response signal ANS to the central processing unit.

In response to this signal, the central processing unit cancels the clock stop, and synchronizes with the clock to send the data DATAxx to the register.
Create a SET.

[Problem that the invention seeks to solve]

In the conventional system as shown in FIG. 3, the main storage device sends out a response signal 5RVO at the timing when data DATAxx for which access has been requested is placed on the bus.

The central processing unit cancels the clock stop and restarts processing in response to the response signal ANS based on the response signal 5RVO. Therefore, even though it is originally possible to take in data at the same time as the response signal 5RVO.

Until the central processing unit actually takes in the data, there will be a loss time from the clock release to the generation of the data capture clock. Note that the clock is not stopped in the case of an access request from the channel device to the main storage device.

Data is captured instantly.

[Means for solving problems]

The present invention aims to solve the above-mentioned problems and provides a means for eliminating loss time when data is fetched from memory in a central processing unit.

FIG. 1 shows a basic configuration block diagram of the present invention.

In FIG. 1, 10 is a central processing unit that fetches and executes instructions and processes data; 11 is a main memory controller;
2 is a main storage device, 13 is a channel device that controls data input/output, 14 is a bus contention control unit that performs priority exclusive control regarding bus use, 15 is a transmitting/receiving circuit that transmits and receives control signals in the main storage device 12, 16 1 is a refresh circuit that sends out a refresh signal to prevent the loss of stored information;
7 is a competition circuit that controls competition between external access and refresh; 18 is a timing generation circuit that generates various control signals in the main memory device 12;

19 is a first response signal sending circuit that generates a first response signal 5RVOI instructing the central processing unit 10 to release the clock stop; 20 is a second response signal that is output in synchronization with the transmission of read data; 5A second response signal sending circuit that generates RVO2, 21 is a dynamic memory (DR
22 is a data transmitting/receiving circuit that transmits and receives data to and from the memory array 21;
represents a data transfer bus.

The main memory device 12 is accessed for read/write by the central processing unit 10 and the channel device W13 via the main memory control device 11, and stores the data. The main storage control device 11 manages the free state/busy state of the data transfer bus 23 using the bus contention control section 14;
The main storage device 12 is controlled in response to an access request from the central processing unit 10 or a DMA request from the channel device 13.

In response to an access request to the main memory device 12, a response signal is sent from the main memory device 12 to the main memory control device 11. In the case of the present invention, in particular, in the timing generation circuit 18, the first response signal sending circuit 19 and The second response signal sending circuit 20 generates a first response signal 5RVOI and a second response signal 5RVO2, respectively, and these signals are sent out via the transmitting/receiving circuit 15.

The first response signal 5RVOI provides timing for canceling the clock stop in the central processing unit 10. The second response signal 5RVO2 is generated at the same timing as the conventional response signal 5RVO explained in FIG. give.

The first response signal 5RVO1 is the second response signal 5RVO
2, it is transmitted in advance by a time corresponding to the time from the release of the clock stop in the central processing unit 10 to the generation of the data capture clock.

[Effect]

After the timing generation circuit 18 is notified of the access request, it applies a control signal to the memory array 21, accesses the memory array 21, and transmits the access data via the data transmission/reception circuit 22.

How long does it take to send data to the data transfer bus 23?

Since it is related to the operating time of the logic circuit, it can be known in advance. Also, in the central processing unit 10.

After receiving a response signal, cancel the clock stop.

The time it takes to generate a data capture clock is also generally fixed and known.

Therefore, before sending out the second response signal 5RVO2, which corresponds to a conventional response signal, the timing generation circuit 18 sends out the first response signal 5RVO2 in advance by a time corresponding to the time from the release of the clock stop to the generation of the data capture clock. response signal 5
Send RVOI.

When the central processing unit IO starts its operation in response to a signal based on the first response signal 5RVO1,
When the data is sent out together with the response signal 5RVO2, the data can be immediately taken in by the data taking clock.

〔Example〕

FIG. 2 shows a time chart according to an embodiment of the present invention.

When reading the contents stored in the main storage device 12, the central processing unit 10 sets an access request in a memory access request register (not shown) under microprogram control in synchronization with the CPU clock. , sends a read access request Read REQ to the main memory control device 11.

After sending the access request Read REQ, the central processing unit 10 stops the clock at a predetermined timing, thereby interrupting the execution of the microprogram, and
Response signal AN according to the first response signal 5RVOI from 2
Wait for S.

The main storage controller 11 uses the bus contention control unit 14 to check the contention state with the channel device 13 and
If no access request has been issued from the central processing unit 10, the access request from the central processing unit 10 Read R11! Attach Q to set busy state CPBSY.

Enters a read sequence related to memory access.

By entering the busy state CPBSY, the main memory control device 11 can access the address of the memory to be accessed.

The memory access request signal SRV i is sent to the main storage device 1.
Send to 2. As can be seen from FIG. 2, one or more operations are the same as in the conventional case.

The main memory device 12 receives the address sent from the main memory control device 11 and the memory access request signal Sl? Vi starts the operation and enters the read sequence of the specified address. Data from the memory array 21 is sampled at a predetermined timing by the timing generation circuit 18, and at the same time as the second response signal 5RVO2 is generated by the second response signal sending circuit 20, the read data DATA
xx is sent to the main storage control device 11.

The first response signal sending circuit 19 receives this second response signal 5R.
Prior to generation of VO2, a first response signal 5RVO1 is generated and sent to the main memory control device 11. Main memory control device 1
1 sends a response signal ANS to the central processing unit 10 upon receiving the first response signal 5RVOI.

In response to this response signal ANS, the central processing unit 10 cancels the clock stop and resumes execution of the microprogram. At the same time, a data capture clock DATA SET for setting memory data is created, and the data DATAx guaranteed by the second response signal 5RVO2 is generated.
Set x to the register.

In the main memory control device 11, the first response signal 5RVO
1, the processing other than sending the response signal ANS to the central processing unit 10 is performed in the same manner as in the past using the second response signal 5RVO2. This completes the series of memory read operations.

As shown in FIG. 2, when the second response signal 5RVO2 is generated, the data acquisition clock DATA Sll!
If T is determined, the memory access time of the central processing unit 10 will be the optimal value.

〔Effect of the invention〕

As explained above, according to the present invention, the response signal from the main memory is divided into two, and the first response signal 5RVOI
and a second response signal 5RVO2 are provided with values that take into account the time from the clock stop cancellation on the central processing unit side to the generation of the data capture clock.

Since the first response signal 5RVOI is sent out first, the data sent at the same time as the second response signal 5RVO2 can be immediately captured, making it possible to shorten memory access time. Become.

[Brief explanation of drawings]

FIG. 1 is a basic configuration block diagram of the present invention, FIG. 2 is a time chart of an embodiment of the present invention, and FIG. 3 is a time chart of a conventional system. In the figure, 10 is a central processing unit, 11 is a main memory control unit, 1
2 represents a main memory, 1 represents a timing generation circuit, 19 represents a first response signal transmission circuit, and 20 represents a second response signal transmission circuit. Patent applicant Hiroshi Mori (1 other person), Patent attorney representing Panafacom Co., Ltd. Figure 3

Claims (1)

[Scope of Claims] The central processing unit (10) includes a main storage device (12) that stores data, and a central processing unit (10) that issues an access request to the main storage device (12). In a main storage device control method in which, when a read request is issued to the main storage device (12), a clock is stopped until a response signal is returned from the main storage device (12) side, the main storage device (12) is a first response signal (SR
VO1) and a second response signal (SRVO2) output in synchronization with the transmission of read data (1).
8), the first response signal (SRVO1) is connected to the second response signal for a time corresponding to the time from the cancellation of the clock stop in the central processing unit (10) to the generation of the clock for data acquisition. (SRVO2), and based on the first response signal (SRVO1), cancels the suspension of the clock in the central processing unit (10), generates a clock for data acquisition, and . A main memory device control method, characterized in that the data transfer bus (23) is released based on the second response signal (SRVO2).