JPS6251493U - - Google Patents
Info
- Publication number
- JPS6251493U JPS6251493U JP14215085U JP14215085U JPS6251493U JP S6251493 U JPS6251493 U JP S6251493U JP 14215085 U JP14215085 U JP 14215085U JP 14215085 U JP14215085 U JP 14215085U JP S6251493 U JPS6251493 U JP S6251493U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- microcomputer
- shift register
- alarm
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002159 abnormal effect Effects 0.000 claims 2
- 230000005856 abnormality Effects 0.000 claims 1
- 238000003708 edge detection Methods 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
Landscapes
- Alarm Systems (AREA)
Description
第１図は本考案の１実施例を示すブロツク図、
第２図は変位点検出部の動作例を示すタイミング
チヤート。
図で、１……入力インターフエイス回路、２…
…タイミングコントロール部、３……エンコーダ
部、４……シフトレジスタ群、５……マイクロコ
ンピユータ部。
FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a timing chart showing an example of the operation of the displacement point detection section. In the figure, 1...input interface circuit, 2...
...Timing control section, 3...Encoder section, 4...Shift register group, 5...Microcomputer section.
Claims (1)
ス回路と、入力された信号が接続される立上り検
出回路と、信号に対応したコードを発生するエン
コード部と、コード信号を保持するシフトレジス
タ群と、データ処理用のマイクロコンピユータと
を具備し、入力信号より分離されたクロツク信号
により異常信号の発生を前記シフトレジスタ内に
保存し、そのデータを読み出し前記マイクロコン
ピユータへ供給することを特徴とする警報診断回
路。 An interface circuit that inputs an alarm signal indicating an abnormality, a rising edge detection circuit to which the input signal is connected, an encoder that generates a code corresponding to the signal, a shift register group that holds the code signal, and a data processing 1. An alarm diagnostic circuit comprising: a microcomputer for storing abnormal signals; the occurrence of an abnormal signal is stored in the shift register according to a clock signal separated from an input signal; the data is read out and supplied to the microcomputer;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14215085U JPS6251493U (en) | 1985-09-17 | 1985-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14215085U JPS6251493U (en) | 1985-09-17 | 1985-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6251493U true JPS6251493U (en) | 1987-03-31 |
Family
ID=31050601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14215085U Pending JPS6251493U (en) | 1985-09-17 | 1985-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6251493U (en) |
-
1985
- 1985-09-17 JP JP14215085U patent/JPS6251493U/ja active Pending
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