JPS6252943A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the size of a chip by providing capacitance elements in all spaces between all bonding pads which are arranged in the circumference of an integrated circuit chip. CONSTITUTION:Bonding pads 4, 4... are arranged in the circumference of an integrated circuit chip divided by scribe lines 7. Further, capacitance elements 1 are provided between respective bonding pads 4. Necessary capacity is distributed to circuit blocks 3, 3, 3 and 3, which are provided at four corners of the chip respectively, by connecting necessary number of the capacitance elements 1 with external wirings 2. In the drawings, the reference numeral 5 denotes an I/O buffer and the reference numeral 6 denotes an internal cell.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit, particularly a diode.

The present invention relates to a master slicing type semiconductor integrated circuit device fK in which elements such as transistors are formed in advance in a chip and various connections between the elements are selected at the stage of vapor deposition wiring to obtain different products.

[Conventional technology]

Conventionally, in the above-described master slice type semiconductor integrated circuit device, the capacitance required in the circuit within the integrated circuit chip has been achieved by forming a capacitive element with a required capacitance value in the vicinity of the circuit that requires the capacitance.

[Problem that the invention seeks to solve]

In the conventional chip capacity arrangement described above, in a master slice semiconductor integrated circuit device that includes many circuits that require capacitance, the ratio of the area of the capacitive element to the effective area for element arrangement within the chip is large; When forming a capacitor that requires a large value, the capacitive element itself naturally becomes large. As a result, there are disadvantages such as an unavoidable increase in chip size, a decrease in the degree of integration, and further a decrease in yield.

[Means for solving problems]

The semiconductor device of the present invention is a master slice type semiconductor integrated circuit device, in which capacitive elements are arranged between all bonding pads arranged around the integrated circuit chip, and these are interconnected by external wiring etc. By using it as the capacitance required in the circuit or for power supply stabilization, it is possible to eliminate the capacitive elements that were previously created near the circuits that require capacitance, and reduce the chip size accordingly. .

〔Example〕

Next, the present invention will be explained with reference to Examples.

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is an enlarged view of the parts within the circles in FIG. In these figures, bonding butts 4, 4 . ... are arranged. Further, a capacitive element 1 is arranged between each bonding pad 4 . Circuit blocks 3, 3, and 3 are provided at the four corners of the chip, respectively.
The capacitance required for 3.3 is distributed to circuit blocks 3 by connecting the required number of capacitive elements 1 with external wiring 2.

Note that 5 indicates an input/output buffer, and 6 indicates an internal cell.

〔Effect of the invention〕

As explained above, according to the semiconductor device of the present invention, the capacitive element formed by the conventional method inside the master slice type semiconductor integrated circuit device is removed, and the pad spacing of the bonding pads arranged around the chip is improved. Since the capacitive element is placed in the chip, the chip size can be reduced and the degree of integration and yield can be improved. Further, depending on the method of connecting these capacitive elements, continuous light capacitance values can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is an enlarged view of the parts within the circles in FIG. 1... Capacitive element, 2... External wiring for connecting the capacitive element, 3... Circuit block requiring capacitance, 4... Bonding pad, 5・・・・・・
...Person output buffer 7a, 6...Internal cell, 7...
...Scripe line. /, - Agent Patent Attorney Susumu Uchihara /, - “K.

Claims (1)

[Claims] 1. A master slice type semiconductor integrated circuit device, wherein a capacitive element is arranged between all bonding pads arranged around the integrated circuit chip.