JPS62532B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display information output circuit in a digital circuit such as a calculator or a microcomputer, and particularly to a glyph information output circuit.

In an information processing device, displaying the processing results is an essential condition. In that case, the processing results are stored in random access memory (hereinafter referred to as
Normally, the data is stored in a main memory circuit such as a RAM (noted as RAM), then sequentially read out, stored in a display memory circuit, and then output as display data through a decoding circuit. At this time, the basic display information is often determined by the number of unit operation bits of the system. For example, in the case of a 4-bit microcomputer, it is most convenient to use 4 bits for display information. This is because calculation processing is performed in a calculator using a BCD code that also uses 4 bits. Therefore, especially in such low-level systems, the types of display information that can be obtained are quite limited. For 4 bits, there are at most 16 types. Therefore, it has been somewhat difficult to obtain display information of 17 or more types. For example, special latches or instructions have been provided to operate the display storage circuitry prior to or concurrently with display information processing operations to achieve the desired purpose. Conventional embodiments will be described below with reference to the drawings.

FIG. 1 shows a conventional embodiment of a display glyph output circuit in a system in which the number of bits per unit operation is 4 bits. In the figure, 1 is a 4-bit parallel logic operation circuit (ALU), 2 is a 4-bit accumulator (Acc) that temporarily stores the operation result of 1, and 3 is a 4-bit parallel logic operation circuit (ALU).
1 is a flip-flop (C) that stores carry information, that is, a carry or borrow, resulting from the operation in 1, and 4 is 4-bit data that transmits the contents of 2 to necessary circuits in the device, such as RAM or output board. 5 is a 5-bit memory circuit that receives the signals 3 and 4 as input; 6 is a decoder that converts the contents of 5 into display glyph information; and 7 is a display device driven by 6. In this example, the fifth bit is obtained from the carry flip-flop 3. The information to be displayed is first subjected to appropriate arithmetic processing in 1 and stored in 2. At this time, carry or borrow information is entered in 3. 2
The information of 4 passes through 4 and is stored in 5 together with the information of 3, resulting in 5 bits of display glyph information. Therefore, in this case, it is necessary to judge each time whether to set 3 or not and perform calculation processing, which would require quite complicated software.

In addition, as the state setting means of 3, there is an example in which 1 is cut off and the state is set or reset by a command prepared in the device in advance. In this case as well, a judgment is required as to whether to set or reset as part of the display process, and the complexity of the software cannot be avoided.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-type display glyph information output circuit with simple display processing.

Another object of the present invention is to obtain a multi-type display glyph information output circuit with a minimum circuit configuration.

According to the present invention, a random access memory (hereinafter referred to as RAM) having at least a plurality of addresses
and a digital circuit including a multi-bit storage circuit for the purpose of transmitting glyph information to an external display device, a decoder that converts the output of the storage circuit into glyph information, and a data bus to which partially displayed information is transferred. , an output information generating circuit is obtained that constitutes all displayed information by a combination of both the address information of the RAM and the partial displayed information on the data bus as input information to the plurality of bits storage circuit.

According to the present invention, address information of a RAM, which is a storage circuit in which information to be displayed is stored, is added as display glyph information input. Therefore, the display glyph information output is determined by the location in the RAM where a portion of the displayed information is stored. That is, in order to transfer the partial display information to the display storage circuit, the RAM address where the partial display information is stored is specified, thereby determining the entire display information. After all, the RAM
The partially displayed information within can be treated as if it were the entire displayed information, which greatly contributes to the simplification of display processing.

The invention and its objects will become clearer from the description taken in conjunction with the following drawings. FIG. 2 shows an embodiment of the present invention. 11 is a parallel arithmetic logic circuit (ALU); 21 is an accumulator (Acc) that temporarily stores the calculation results of 11; and 41 is a transmitter that transmits the contents of 21 to necessary circuits in the device, such as RAM or output ports. A data bus 101 is a multi-bit data bus in which operand processing information is stored.
RAM, 81 is an address bus through which address information specifying an address within 101 is transmitted, 91 is 8
a decoder that converts the contents of 1 into a concrete address;
Further, 51 is a display information storage circuit which inputs the contents of 41 and 81, 61 is a decoder that converts the contents of 51 into display glyph information, and 71 is a display device driven by 61. In this example,
The contents of the accumulator and
RAM address information is used. The contents of the accumulator and the contents of the RAM address information are combined to form one piece of displayed glyph information, and this information is converted into actual displayed glyph information by a decoder 61. Assuming that 41 is a 4-bit bus, if only these 4 bits are used to provide display glyph information, only 16 types of display glyph information can be obtained at most. However, as shown in this embodiment, by adding RAM address information to the 4-bit information, display information can be expanded within a range proportional to the amount of address information. At this time, if the address of the partial display information stored in 21 via 11 is used as RAM address information, the desired display glyph can be selected based on the storage address in the RAM. Therefore, an output information generating circuit is constructed in which display processing is extremely simple and the circuit configuration is also simple. Note that by performing appropriate calculations in step 11, display processing with appropriate conversion can also be executed.

As explained above, according to the present invention, a wide variety of display character shapes can be obtained with extremely simple hardware, so it is especially suitable for digital circuits using integrated circuits and the like.

In this embodiment, 21 pieces of partial display information are used.
Although the Acc output was used, it goes without saying that the same result can be obtained by directly using the ALU output of 11 or the RAM output of 101.

Furthermore, it goes without saying that even if the output of the decoder 91 is used as the address information, exactly the same result can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an example of a conventional display glyph information output circuit. FIG. 2 shows an embodiment of the display glyph information output circuit according to this patent. 5...Displayed information storage circuit, 6...Decoder,
51...display information storage circuit, 61...decoder, 81...RAM address information.

Claims (1)

[Claims] 1 A memory having multiple addresses, a multiple-bit storage circuit for storing displayed information, a decoder that converts the output of the storage circuit into display output information, and a data bus to which partial displayed information is transferred. The output information generating circuit is characterized in that the total display information stored in the multi-bit storage circuit is configured by a combination of both the address information of the memory and the partial display information on the previous data bus.