JPS6256018A - Complementary type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To save the power consumption by providing plural complementary dynamic inverter circuits and a static complementary level converting circuit. CONSTITUTION:An input signal is fed to an input line N2 from a complementary circuit receiving a low power voltage VDD. A clock signal having a large amplitude between zero V and a high power voltage VGG fed to a source of a MISFET Q1 is applied to a clock signal line N1. The large amplitude clock signal is applied from a level converting circuit receiving a signal outputted from a clock signal generating circuit activated by, e.g., a low power voltage. The level converting circuit consists of n-channel MISFETs Q4, Q6, p-channel MISFETs Q5, Q7 and a complementary inverter circuit IV1. Thus, the level conversion circuit with low power consumption is offered.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary semiconductor integrated circuit including a level conversion circuit formed of complementary insulated gate field effect transistors (hereinafter referred to as MISFETs).

A logic circuit configured with complementary MISFETs exhibits low power consumption characteristics because its operating current flows substantially only during the transition period of signal change. The above operating current can be further reduced by lowering the power supply voltage.

For example, in semiconductor integrated circuits used in electronic desktop calculators that include liquid crystal display devices, complementary logic circuits that perform various logical operations such as addition and subtraction on one side are needed to further reduce overall power consumption. On the one hand, the complementary logic circuit driving the liquid crystal display can be operated at a relatively high voltage so as to generate a signal at the level required by the liquid crystal display. .

However, in the above case, the high-voltage complementary logic circuit requires an input signal with a level amplitude corresponding to the power supply voltage, so the high-voltage complementary logic circuit can be used with the low-voltage complementary logic circuit. An appropriate level conversion circuit for driving is required.

Therefore, an object of the present invention is to provide a level conversion circuit suitable for complementary logic circuits.

Another object of the present invention is to provide a level conversion circuit that occupies a small area in a semiconductor integrated circuit and has low power consumption.

Another object of the present invention is to provide a level conversion circuit that uses fewer MI 5FETs.

Further objects of the invention will become apparent from the following description and drawings.

According to the invention, a complementary dynamic inverter circuit is used as a level conversion circuit.

Hereinafter, this invention will be explained in detail based on examples.

FIG. 1 shows a circuit of an embodiment of the invention. In the figure, Q is an enhancement mode n-channel MISFET, whose source and base gate are connected to a power line N, which receives a high power supply voltage VCC such as -4 or 5 volts, and whose gate is connected to a Glock signal line. N, and its drain is connected to the output line N4.

Qt and Q are enhancement mode p-channel type MI 5FETs, among which MI 5FETQ!
has its drain connected to the output line N, its gate connected to the input line N, and its substrate connected to the circuit ground point E.
It is connected to the. The above MISFETQ has its drain connected to the above MI5FETQ! The gate is connected to the clock signal line N, and the source and the base gate are connected to the ground point E.

An input terminal of a complementary static inverter circuit IV receiving power supply voltage VGG is connected to the output line N4. The inverter circuit IV is composed of an enhancement mode n-channel WMISFETQ and a p-channel MISFETQ9, as shown in FIG. 4 tbl corresponding to the symbols in FIG. 4 1al.

Input line N has a low supply voltage such as -1.5 volts.
An input signal is supplied from a complementary circuit receiving the DD, such as a complementary static inverter circuit (not shown).

The clock signal line N is supplied with a large-amplitude clock signal having one level of yO volts and the other level reaching the high power supply voltage "GG" applied to the source of the MISFET QI.

The above-mentioned large-amplitude clock signal is supplied, for example, from a level conversion circuit as shown in FIG. 3, which receives a signal output from a clock signal generation circuit (not shown) operated by a low power supply voltage.

The level conversion circuit shown in Fig. 3 is an n-channel type MIS.
FET Q4 + Qe, p-channel MIS
FETQs,Q? and complementary inverter circuit IV.

It consists of The MIsFETQ receives a signal having a phase opposite to the signal applied to the input line Nv via the inverter circuit Ivl and the line N. The above n-channel type MISFETQ4 has a MISFETQ at its gate.
, and Q receive a signal on the output line N6 connected to them. Similarly, MISFETQ has MISFET on its gate.
E.T.Q.

and Q, receive a signal at the output line N, to which they are connected.

The level conversion circuit shown in FIG. 3 uses a low voltage system input signal I.
In response to the inverted input signal of the other voltage switch output from N and the inverter circuit IV, a high voltage system signal in the same phase as the input signal IN is output to the output line N6, and a high voltage system signal of the opposite phase is output to the output line N. Outputs the signal.

In FIG. 1, power supply voltages VCO and VDD are negative voltages. Correspondingly, although not particularly limited, the high level of the signal may correspond to, for example, O volts of the y-ground potential;
Low level is g power supply voltage. .

Or it can be made compatible with VDD.

MISFETQ+ is used as a precharge means for the capacitance C between the output line N4 and the ground point E, and MISFET
FETQ is used as a discharge means for the capacitor C.

That is, when the clock signal φ is set to a high level of XO volts, the MI 5FETQ+ is turned on,
The above capacity C! 1" Charge to the power supply voltage VCC. At this time, MISFETQs is in the off state, so MISFETQ+ to Q.

It is prohibited that a through current path be formed in the

Is the clock signal φ3j? ! When the E source voltage is set to a low level, MISFETQ is in the off state, and MISFETQs
be turned on. At this time, if the input signal IN is at a high level of the y ground potential, MISFET Q2 is in an off state. At this time, a discharge path is not formed for the capacitor C, and therefore the potential of the output line N4 varies depending on the capacitor C.
The power supply voltage is maintained at VGG. Conversely, the input signal IN is
I-+MISFETQ, where the i source voltage VDD is at a low level, is turned on, and the charge in the capacitor C is discharged.

As a result, the potential of the output line N4 is set to the high level of the y ground potential.

In other words, for the input signal IN of the low voltage system, the output line N4
A high voltage system output signal is output. An inverted signal of the signal on the output line N4 is output from the high voltage complementary static inverter circuit IV.

In the level conversion circuit of FIG. 1, the output signal level is not affected by the conductance characteristics of MISFETQ+ to Q.

In the level conversion circuit shown in FIG. 3, MISFETs Q and Q are connected in series between the original line N and the ground point.
The signal level of the output line N is determined by the conductance ratio between the MISFETs Q and Q, and the signal level of the output line N is determined by the conductance ratio of the MISFETs Q and Q. In order to output a signal with amplitude, MI 5FETQ= , Qs
M I S F E T
It is necessary to make Q4 larger than Qe. Therefore, a relatively large occupied area is required in the semiconductor integrated circuit. Furthermore, as the stray capacitance of the circuit increases due to the large occupied area, the amount of charge to be charged and discharged increases, so the power consumption is relatively large.

However, the level conversion circuit shown in FIG. 3 used to output a clock signal can be shared by a plurality of level conversion circuits shown in FIG. 1.

Therefore, even if the level conversion circuit of FIG. 3 is used, the area required in the semiconductor integrated circuit can be reduced.

MISFETQ for discharge shown in FIG. 1 above, and
The input MISFETQ may have a connection relationship reversed to 5 as shown in FIG. Furthermore, when using a positive power supply voltage (Vcc*VDD), a p-channel MISFET is used as a precharge means, and an n-channel MISFET is used as a discharge means and an input means.

FIG. 7 is a logic circuit diagram showing an embodiment in which the present invention is applied to a display drive circuit in an electronic desktop calculator.

This circuit operates with a low supply voltage of -1.5 volts, display register section A, ~i? and this signal level is -4,5
Level converter circuits B1 to Bt1 convert signal levels to high power supply voltages of volts, static flip-flop circuits C0 to CUt and this flip-flop circuit Cl-, which input the level conversion output and hold large-level display signals. C1? Driver D receives the output of =-D□
It consists of

The display register A for the 1-bit signal includes a clocked inverter circuit IV that takes in display data at the timing of the shift clock pulse φ1, a static inverter IV, and a clocked inverter IV that operates in an opposite phase to the inverter IV. , a clocked inverter IV4 that takes in the output of this flip-flop circuit at the timing of a shift clock pulse φ, and this clocked inverter Iv.
and a static inverter IV which outputs a signal to the next stage based on the output signal of No. 4.

The clocked inverter IV is, for example, 5 as shown in FIG.
n-channel type MIS which receives gate 9 input signal IN
Consisting of FETQ+o and p-channel type MISFETQ+i, p-channel type MISFETQ+t whose gate receives shift clock pulse φ1, and n-channel type MISFETQ whose gate receives shift clock pulse φ1 having the opposite phase of the shift clock pulse φ. has been done. In this clocked inverter IV,
When the shift clock pulse φ, becomes the yt source voltage VDD, and φ, becomes the y ground potential, the MIS
Since FETQII and Q+t are turned on, the inverted signal of the input signal IN is output as the output signal OUT. /
When the clock pulse φ1 is set to the y ground voltage and φ1 is set to the power supply voltage, the above MISFET Qo
, QH are turned off. At this time, the output signal OUT
is held by capacitance C8 in the output line.

The clocked inverter IV is configured as shown in FIG.
．． With respect to φ, the clock inverter IV operates in a manner opposite to that of the clock inverter IV. That is, the clocked inverter IV takes in the input signal when the shift clock pulse φ1 is at the ground potential and when the voltage is at the power supply voltage VDD.

Note that a clocked inverter configured to take in an input signal at a high level of a clock pulse, such as clocked inverter IV above, is shown with a different symbol from other clocked inverters in FIG. 7 for easy identification. has been done.

The static inverters I Vt and I Vs are constructed as shown in FIG.

Clocked inverter IV is the same as clocked inverter I, except that the shift clock pulse is φ2.
It has the same configuration as v1.

Next shift register A! The shift register AI also has a configuration similar to that of the shift register AI described above. This shift register person is
The output of the shift register A1 is connected in series with the shift register A1, i.e., the static inverter I
It receives the output of V.

Similarly, shift registers A to A27 are connected in series.

The above shift clock pulse φ3. φ, is Fig. 8A +
As shown in B, alternately set the voltage to the low level of the power supply voltage VDD. The input signal IN is changed in synchronization with the shift clock pulse φ, as shown in FIG. 8F.

When the shift clock pulse φ1 becomes low level at time t1, the clocked inverter IV enters the operating state, takes in the input signal IN, and outputs the eighth signal to its output line a.
Output a signal like figure G. In response to the output signal of the clocked inverter IV, the static inverter IV outputs a signal as shown in FIG. 8H to its output line. At this time, clocked inverter IV is in an inactive state and does not affect the output signal of clocked inverter IV.

At time t, when the clock pulse φ is returned to the high level of the ground potential, the clocked inverter IV becomes inoperative, and the clocked inverter IV
becomes operational. The clocked inverter IV3 constitutes a positive feedback circuit for the static inverter IV.

As a result, the signals input from the clock inverter V are input to the inverters IV and IV.

It is held in a flip-flop circuit consisting of.

When the shift clock pulse φ is brought to a low level at time t, the clocked inverter IV.

enters the operating state, takes in the signal from the above-mentioned 7 rigfx circuit, and outputs a signal as shown in FIG. 8I to its output line C. In response to the output signal of the clocked inverter Iv4, the static inverter IVg outputs a signal as shown in FIG. 8J.

At time t, when the /futochronograph pulse φ1 is brought to a low level again, a new input signal IN is taken into the clocked inverter IV. At the same time, the signal held in clocked inverter IV is taken in to clocked inverter IV to of the next stage shift register At via static inverter IV.

Level conversion circuit B or B2? are each shift register A1 to A7 . 1 and 2, respectively.

The above level conversion circuit B or Bl? Is the display data in the shift register A, A, or A? and then the output flip-flop circuits C1 to C! Data is taken in from the above-mentioned corresponding soft register A or person 7 until the start of data taking in data.

Therefore, although not particularly limited, the clock pulses for each of the level conversion circuits B, B, 7 are set as shown in D in FIG. 8. This clock pulse φ,' is, for example, a shift clock pulse φ.

The shift clock pulse φ2 after display data has been taken into all shift registers A1 to kzl by
a low-voltage logic circuit (not shown) that outputs a valve switch signal g as shown in FIG.
When the pulse signal is at a low level, the shift clock pulse can be generated by a low-voltage gate circuit (not shown) that transfers the shift clock pulse, and a level conversion circuit shown in FIG. 3 that receives the output signal of the gate circuit. can.

Each level conversion circuit B1 to B2. The capacitance in each output line of is determined by the clock pulse φ□ as shown in Figure 8.
' becomes the high level of the y ground potential at time t, so that it is precharged as shown in the figure. At the time t1 of the tarok pulse φ,', the temperature is y and the critical voltage VGG.
By becoming a low level, the output line potential of each of the level conversion circuits B to B7 can be determined according to the low voltage system signal supplied from the corresponding shift register A to A Ig. .

The output flip-flop circuit C1 includes clocked inverters IV, IV9 and a static inverter Iv. Each of the above inverters IV7 to IV,
are the inverter IV of the shift register A1, respectively.
, to IV3. While the inverter IV or IV is operated by a low power supply voltage VDD, the inverter IV or IVs
is operated by a high supply voltage vGG.

Output flip flop circuit C2 or C! , has the same structure as the above flip-flop circuit C1.

The clock pulses φ,' supplied to the output flip-flop circuits C3 to C17 are high voltage signals.

This tarock pulse φ1' is obtained by sampling the shift clock pulse φ shown in FIG. 8A using the gate signal shown in FIG.

At time t, the tarlock pulse φ1' is equal to the supply voltage g. When G is set to a low level, the clocked inverter IV7 takes in the output signal of the level conversion circuit B1 and outputs a signal as shown in the eighth diagram to its output line f.

The output vanofer circuit outputs a signal corresponding to the output signal of the output flip-flop circuit CI.

Similarly, the output vanofer circuits C1 to Cwt output signals corresponding to the output signals of the corresponding output flip-flop circuits C1 to Cwt, respectively.

The output signal of the output vanofer circuit 7 is as follows:
These are supplied to the electrodes of the liquid crystal display device via terminals a and co, respectively.

For example, as shown in FIG. 10, a liquid crystal display device includes common electrodes E, E, segment electrodes a to g for displaying numbers arranged in the shape of a Japanese character on the common electrodes E, E, and a decimal point. It consists of a plurality of units consisting of display segment electrodes. Lines al through C0 provided in the liquid crystal display device of FIG. 1C are connected to terminals with corresponding symbols in FIG. 7.

A line B provided to the common electrode E1 or E,
A predetermined signal is supplied to the circuit from another circuit (not shown). Desired numbers dynamically select common electrodes and segment electrodes,
This is done by applying a voltage of a predetermined value or more between the common electrode and the segment electrodes.

In this example, the timing signal φ,′.

In order to form φ1', the level conversion circuit B which occupies a large area and consumes a large amount of power as shown in FIG.
~B! ? As shown in Fig. 1 or 2, it is composed of three relatively small MISFETs Q, ~Q3, so when using 27 level shift circuits shown in Fig. 3 above, For example, if the chip area is 115
It can be significantly reduced to ~1/7, and since no direct current flows, it is possible to significantly reduce power consumption.

Therefore, the level conversion circuit according to the present invention has a great advantage in a complementary MIS logic circuit having a large number of level conversion circuits.

Note that the output flip-flop circuits CI to C! ? teeth,
Since it has a clocked inverter IV that takes in an input signal, it can be modified to use the inverter shown in FIG. 1 having a level conversion function, as shown in FIG.

If such a static flip-flop circuit is used in the display drive circuit shown in FIG. 7, the level conversion circuit IL-E3tt can be omitted, resulting in smaller chip size and lower power consumption. be able to. This embodiment circuit can be widely used as a flip-flop circuit having a level shift function or a level shift circuit having a latch function.

Brief description of the drawing FIG. 1 is a circuit diagram of a level conversion circuit according to an embodiment.

FIG. 2 is a circuit diagram of a level conversion circuit of another embodiment, FIG. 3 is a circuit diagram of a static operation level conversion circuit, and FIG.
Figure 1al is a logical symbol diagram of a static inverter, Figure 1bl is a specific circuit diagram of an inverter corresponding to Figure 1al, Figure 5 1al is a logical symbol diagram of a clocked inverter, FIG. 6 1al is a logic symbol diagram of another clocked inverter, FIG. 6 fbl is a specific circuit diagram of the inverter shown in FIG. A logic circuit diagram of one embodiment of the present invention applied to this case, FIG. 8 is an operation waveform diagram of the circuit of FIG. 7, FIG. 9 is a circuit diagram of another embodiment of the present invention, and FIG. 10 is a liquid crystal display. FIG. 2 is a plan view of the device.

A, %A,...shift register, B, ~Bt□...
・Level shift circuit, C8-C1? ... Output flip flow IE 2nd room 3rd
Figure 4 Solid layer Figure 7 Figure 8 Figure 9 Figure h' Figure 10

Claims (1)

[Claims] A plurality of complementary dynamic inverter circuits each receiving a low-voltage input signal and outputting a high-voltage signal, and a high-voltage circuit receiving a low-voltage pulse signal and controlling the plurality of complementary dynamic inverter circuits. 1. A complementary semiconductor integrated circuit comprising: a statically operated complementary level conversion circuit for forming a system pulse signal.