JPS6256539B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an information processing device having a test function. Recently, due to advances in semiconductor technology, the number of elements integrated on the same substrate has increased significantly. For this reason, testing methods for determining the acceptability of integrated circuits (LSI) in which a large number of elements are integrated become a problem. In particular, special test circuits and test functions are required for single-chip microcomputers with a built-in read-only memory (ROM) or LSIs that have internal timer functions that count extremely long times. That is, in the former case,
Even if the contents of the ROM have various different patterns, it would be convenient if parts other than the ROM (for example, the arithmetic section and the control section) could be determined to be good or bad using the same test method. Also, in the latter case, for example, in the case of an LSI that has a built-in timer (counter) that counts several hours, it takes several hours to test this timer, resulting in a decrease in work efficiency. become. Therefore, in order to test such an integrated circuit, conventionally, a test circuit as shown in FIGS. 1 and 2 has been provided in order to shorten the test time. The circuit shown in FIG. 1 is a timer circuit that can measure up to one hour with a test function. The timer circuit with test function shown in Figure 1 is 1k
The clock signal CLOCK with a frequency of Hz is 1Hz.
A frequency dividing circuit 1 that divides the frequency signal into a frequency signal of The counters 5 are connected in series, and a switching circuit 6 is inserted in each connection.
As shown in FIG. 2, this switching circuit 6 has two AND gates 7 and 8 and an OR gate 9 to which its output terminal is connected. The output from the counter or frequency divider circuit and the test signal input from the test terminal inverted via the inverter 10 are input,
A 1 kHz clock signal and a test signal are input to the input terminal of the AND gate 7, and the output from the OR gate 9 is added as an input signal to the next stage counter. The normal operation of such a timer circuit is carried out in a state where the test signal C is not input from the test signal input terminal, and the clock signal B input to the AND gate 7 of the switching circuit 6 is inhibited, and the clock signal B input to the AND gate 8 is inhibited. The output from the frequency dividing circuit 1 and the output A from each counter 2, 3, and 4 are allowed to be input to the next stage counter. Therefore, the second counter 2 counts the number of input 1 Hz signals and outputs a carry signal A to the 10 second counter 3 every 10 signals. Furthermore, the minute counter 4 inputs the carry signal A of the 10 second counter 3,
Every time 10 pieces are counted, carry signal A is sent to 10 minute counter 5.
Output to. Each counter receiving these signals sends a predetermined signal state to a display section or the like and performs a timer operation. On the other hand, when the test signal C is input from the test terminal, the switching circuit 6 prohibits the input of the carry signal A and simultaneously outputs the 1 kHz clock signal B to each counter 2 to 5. Therefore, each counter is tested simultaneously and with a high frequency signal of 1 kHz, significantly reducing test time. If the test circuit consisting of the switching circuit 6 and the test terminal is not inserted into the timer, it will take at least one hour to check whether the timer circuit is normal. Therefore, by providing the test terminals and the switching circuit 6 as shown in FIG. 1, the LSI can be tested at high speed. However, there is a major drawback in that an additional test terminal that is unnecessary during actual operation must be provided. Advances in semiconductor technology have made it possible for LSIs manufactured in recent years to have extremely high functionality. and,
These LSIs require more terminals as they become more sophisticated, so it is desirable to omit terminals that are not needed during operation, even if they are for testing. An object of the present invention is to provide an information processing device that can perform high-speed test processing and does not require a test terminal. The present invention provides an information processing device having a circuit under test and a plurality of input terminals into which a plurality of control signals for controlling the circuit under test are input in a normal state. By providing a state setting circuit that is set and reset when different combinations of signal groups are input, when the state setting circuit is set, it tests the circuit under test, and when it is reset, it ends the test. , is characterized by omitting an input terminal for inspection instructions. Hereinafter, a case where an embodiment of the present invention is applied to a timer circuit capable of counting one hour will be described with reference to FIGS. 3 and 4. Figure 3 is a block diagram of a timer circuit with a test function.The 1/1000 frequency divider circuit 10 divides the 1kHz reference clock signal CLOCK to 1Hz, that is, outputs 1 clock for every 1000 clocks input.
, seconds digit counter 11, and 10 seconds digit counter 12
The minute digit counter 13 and the ten minute digit counter 14 are configured as switching circuits 15-1 and 15- as shown in FIG.
2, 15-3, and 15-4 are connected in series. On the other hand, the frequency dividing circuit 10 and each counter 11 to 1
4 are respectively connected to a control circuit 17, and this control circuit is also connected to a flip-flop circuit 18 for holding signals and a buffer circuit 16 for inputting input signals I ₁ and I ₀ under the control of a selection signal CS. and is configured to be able to send control signals to each circuit. However, unlike the input terminal C of the switching circuit shown in FIG. 2, the output signal OUT from the flip-flop 18 is input to the input terminal C of the switching circuit 15 applied in FIG. 3. In the same figure, signals that give commands to the control circuit 17 are input to two input terminals I ₀ and I ₁ , and CS
is a chip select terminal that takes the command into the control circuit 17 via the buffer 16;
CLOCK is a reference clock input terminal of 1 KHz, and each counter 11-14 outputs 4-bit coded signals A, B, C, and D indicating their respective states to the outside. The circuit diagram shown in FIG. 3 is applied to a part of the device as shown in FIG. 4, for example, and the timer circuit 22 is
It is connected with the CPU 20, memory 21, etc. by a bus 24, and the output from each counter is connected to the bit line A,
The signal is output to, for example, the display unit 23 via B, C, and D, and displays the time or time. Therefore, the input signals I ₁ and I ₀ are 2-bit instructions read from the memory 21 or the like according to instructions from the CPU 20 or I/O.
CS becomes the selection signal input terminal. Here, it is assumed that the input signals I ₁ and I ₀ have the command system shown in Table 1 below.

[Table] In Table 1, the timer starts counting when (I ₀ , I ₁ ) = (0, 0), and stops counting when (1, 0) is input. Moreover, the timer is set to the test state by inputting (0, 1), and the test is ended by inputting (1, 1), and the counter and frequency dividing circuit are set to the initial state. The operation of FIG. 3 will be explained below. When one of the commands in Table 1 is given to the I ₀ and I ₁ terminals from the memory or peripheral device, and CS becomes “H”, the command given to the I ₀ and I ₁ terminals is sent to the control circuit 17. It will be done. The control circuit 17 interprets and executes the instructions. For example, if the command "START" (0, 0) is given, the control circuit 17 controls the frequency dividing circuit 10, each counter 11 to
14, then instructs them to start counting or frequency division. When the frequency dividing circuit 10 is instructed to start frequency division, the 1K input from the CLOCK terminal
The frequency of the Hz clock is divided and a 1 Hz clock is output to the switching circuit 15-1. At this time, the output of the flip-flop 18 becomes "0", the switching circuit selects the divided signal input to the terminal A, inputs the 1 Hz second signal to the second counter 11, and from the second counter 11,
A 1/10Hz signal is output to the 10 second counter 12 via the switching circuit 15-2. Similarly, counter 1
3 and 14 are input with 1/60Hz and 1/600Hz signals, respectively. Each counter displays the contents of the counting results.
The coded signals are output to the display section via the bit lines Ai, Bi, Ci, and Di (i=1, 2, 3, 4). Next, when a "STOP" command (1, 0) is input to the input terminals I ₀ and I ₁ and CS is set to "H", the control circuit 17 causes the counters 11 to 14 to stop counting. Therefore, in this state Ai, Bi,
By checking Ci and Di (i=1, 2, 3, 4), it is possible to count the time from when the "START" command is input until when the "STOP" command is input. On the other hand, the flip-flop 18 indicates the test state and is set by the "TEST SET" command (0, 1) and outputs "H" from the output, indicating the "TEST SET" command (0, 1).
This is a memory circuit that is reset by the "TEST SET" command (1, 1). When the "TEST SET" command (0, 1) is input to I ₀ and I ₁ and CS becomes "H", the control circuit 17 is reset through the buffer 1. The control circuit 17 interprets the command and sets the flip-flop 18. Therefore, the switching circuit 1
Since "H" is input to the C terminals of 5-1, 2, 3, and 4, the 1KHz clock signal input from the B input terminal is simultaneously output to each counter. When a "START" command (0,0) is input in this state, that is, in a state in which the test state flip-flop is set, each counter is reset once and then starts counting at the 1 KHz clock simultaneously. Therefore, it can be checked in a short time whether each counter is operating normally. Furthermore,
When the "TEST RESET" command (1, 1) is input, the flip-flop is reset and the signal input to the A input terminal of each switching circuit is output to output terminal 0. Output is input. Therefore, each counter can accurately measure time. In this way, by providing an internal test state flip-flop that can be set and reset by a command, the internal circuit can be efficiently tested at high speed without providing a TEST terminal. Although one embodiment of the present invention has been described above,
The clock signal (1KHz) used in this example is not specially provided for the timer circuit;
Other control systems, processing systems (e.g. memory control, CPU
However, the invention is not limited to this clock signal. Furthermore, the configuration of the switching circuit is not limited to that shown in Fig. 2, and various configurations such as various logic circuits, gate circuits, switch means, decoder circuits, etc. can be considered, and the flip-flop that indicates the test state also has a memory retention and output function for a predetermined period of time. As long as it is possible,
A shift register etc. can also be used instead. Of course, the configuration of the device is not limited to a one-chip microcomputer, but can be any system in which each component is formed on a single chip, and the present test mechanism is not limited to a timer.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional timer having a test function, Fig. 2 is a logic block diagram showing an example of a switching circuit, and Fig. 3 is a block diagram of an embodiment of the present invention applied to a timer circuit. In the figure, FIG. 4 is a system configuration diagram showing a part of an information processing apparatus having a test function of the present invention. 1, 10... Frequency divider circuit, 2, 3, 4, 5, 1
1, 12, 13, 14...Counter, 6, 15...
...Switching circuit, 16...Buffer circuit, 17...Control circuit, 18...Flip-flop.

Claims (1)

[Claims] 1. In an information processing device having a circuit controlled by signals inputted from first and second input terminals, a signal of a combination different from the signal controlling the circuit is inputted to the first and second input terminals. 1
a flip-flop that is set when a second signal of a different combination is input, and reset when a second signal of a different combination is input; An information processing device characterized in that: