JPH1021101A - Microcomputer device - Google Patents

Abstract

(57) [Summary] [Problem] Even when the speed of a clock supplied to a CPU is irregular or the speed of a clock supplied to peripheral hardware is irregular, this is accurately determined. And a microcomputer device having a diagnostic function. SOLUTION: A measurement time measured by executing a predetermined program by a CPU with reference to a clock supplied through a first clock supply system, and a measurement time supplied through a second clock supply system. The measured time is compared with the time measured by the timer circuit on the basis of the clock which is used as a reference, and the presence or absence of abnormality is determined based on the result of the comparison.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device having a built-in self-diagnosis function, and more particularly to a microcomputer device based on a comparison result of a measurement time measured by a so-called hardware timer and a measurement time measured by a software timer. The present invention relates to a microcomputer device having a function of diagnosing the presence or absence of an abnormality.

[0002]

2. Description of the Related Art A microcomputer device of this type includes a so-called one-chip microcomputer in which circuit elements such as a CPU, a ROM, a RAM, and peripheral hardware are integrated into one chip, What is called a so-called microcomputer board or the like in which are mounted on a single circuit board as individual components are known. In any of the microcomputer devices having the above configurations, the operation clock for the CPU and the operation clock for the peripheral hardware are generally supplied through separate clock supply systems. This is because the operation time of the CPU does not always coincide with the operation time of the peripheral hardware.

That is, a clock generated from an external crystal oscillation circuit or the like is adjusted to an appropriate speed via a main system clock generation circuit, and then a clock supply system to the CPU and a clock supply to peripheral hardware. Sent to the system. These clock supply systems are used to select a prescaler for generating a plurality of clock signals having different division ratios based on a given clock, and to select one of the plurality of clocks generated from the prescaler. And the like are included.

By the way, as means for diagnosing abnormal operation in this type of microcomputer device,
A failure diagnosis method using a so-called watch dog timer circuit has been conventionally known. In this failure diagnosis method, an ON signal and an OFF signal are supplied to a specific output port in a control program in which a cycle execution time is specified in advance.
While a port ON command and a port OFF command are inserted so as to output signals alternately, the period of a periodic pulse train obtained from this output port is monitored by a watch dog timer. Is forcibly reset.

[0005]

However, in such a fault diagnosis method using the conventional watch dog timer circuit, if the reliability of the microcomputer device is to be extremely pursued, the CPU and the CPU need not be used. It is necessary to confirm that a clock of a specified speed is normally supplied to each of the peripheral hardware. That is, the clock speed deviation often occurs when bits are fixed in a frequency dividing circuit, a selector, or the like constituting each clock supply system.

An object of the present invention is to provide a method for controlling the speed of a clock supplied to a CPU or the speed of a clock supplied to peripheral hardware. An object of the present invention is to provide a microcomputer device having a function of accurately diagnosing this.

[0007]

According to a first aspect of the present invention, there is provided a CPU for executing a program, a timer circuit usable through the program,
A microcomputer device comprising: a first clock supply system for supplying a clock to a PU; and a second clock supply system for supplying a clock to peripheral hardware including the timer circuit. The system program of the microcomputer device incorporates a diagnosis process for diagnosing a state of the microcomputer device, and the diagnosis process is performed by a clock supplied through the first clock supply system. The measurement time measured by executing a predetermined program in the CPU with reference to the measurement time measured by the timer circuit with reference to the clock supplied through the second clock supply system. Collating and determining whether there is an abnormality based on the collation result. In the over the other apparatus.

According to the first aspect of the present invention, the measurement is performed by executing a predetermined program by the CPU with reference to a clock supplied via the first clock supply system (so-called software). The measured time (measured by the timer process) is compared with the measured time measured by the timer circuit (measured by the so-called hardware timer) with reference to the clock supplied through the second clock supply system. Then, the presence or absence of an abnormality is determined based on the collation result.

Here, the comparison of the measurement time measured by the hardware timer processing with the measurement time measured by the software timer processing may be performed based on any of them. In other words, the timer circuit measures a certain period of time, and when a timer interrupt occurs, the measurement time of the software timer may be read and compared with each other. Alternatively, the fixed time may be measured by the software timer process. In response to this, the measurement time of the hardware timer may be read, and the two may be compared.

[0010] Note that "CP for executing a program"
"U" is merely a comprehensive definition of general functions in this type of CPU. That is, in this type of CPU, generally, instructions are sequentially read from a ROM or the like while a program counter is incremented, and this is read out by A
The functions defined by the program are realized by executing the program using an LU (Arithmetic and Logical Unit) or the like.

The "timer circuit which can be used via a program" means that in this type of microcomputer device, several command words for using an external timer circuit are prepared in advance. Arbitrary time can be measured using those command words. Here, as is well known, the measurement time in this type of timer circuit can be read into the CPU at any time by using a predetermined instruction word.

The term "peripheral hardware including a timer circuit" includes various hardware circuits for supporting the operation of the CPU in addition to the timer circuit in this type of microcomputer device. Since these are customary, they are comprehensively defined. According to the first aspect of the present invention, if any of the frequency dividing circuits and the selectors constituting the first clock supply system and the second clock supply system has a bit fixation failure, etc. 2 based on the clock supplied via
Since there is a difference between the two measurement times, the presence or absence of an abnormality can be determined based on the result of the comparison.

According to a second aspect of the present invention, there is provided a CPU for executing a program, a timer circuit usable via the program, and a first circuit for supplying a clock to the CPU. A microcomputer device comprising a clock supply system and a second clock supply system for supplying a clock to the timer circuit, wherein a system program of the microcomputer device includes a state of the microcomputer device. A diagnostic process for diagnosing the timer is incorporated. The diagnostic process includes a timer circuit activation process for activating the timer circuit to perform a clocking operation, and a predetermined process that is activated almost simultaneously with the activation of the timer circuit. Software timer processing for measuring the target time of In response, the elapsed time of the timer circuit is read, a collation process for collating this with the target time of the software timer, and a determination process for determining the presence or absence of an abnormality based on the collation result in the collation process, A microcomputer device characterized by the above-mentioned.

According to the second aspect of the present invention, the measurement time measured by the software timer processing is used as a reference, and the measurement time measured by the hardware timer processing is read and compared with each other. The presence or absence has been determined.

Here, "almost at the same time as the activation of the timer circuit" means that it is difficult to activate both at exactly the same time from the principle of microcomputer processing which is a serial execution method. It is. Of course, these activations are most preferably performed with a delay of one instruction execution time.

As described above, since "the time measured by the timer circuit is read in response to the completion of the time measurement operation in the software timer process", as described above, in this microcomputer device, As is generally known, by using a predetermined instruction word at an arbitrary time, it is possible to read the measurement time of the external timer circuit.

The expression "determining the presence / absence of an abnormality based on the result of the collation in the collation process" means that the presence / absence of an abnormality is determined based on whether the collation matches or does not match. Is determined, a certain allowable width is set. In other words, no matter how both clocks are normal, it is unlikely that the measurement times measured in the two measurement systems completely match in bit units.

According to the second aspect of the present invention, since the collation processing of both measurement times can be performed without activating the timer interruption processing, the collation reliability of the measurement time is improved.

According to a third aspect of the present invention, in the microcomputer device according to the first or second aspect, the diagnosis processing is executed by an initialization processing in a system program. is there.

According to the third aspect of the present invention, the above-described diagnosis processing is executed by an initialization processing in a system program.

Here, the "initialization process" is a process executed immediately after power-on and before shifting to the original control program, as is well known to those skilled in the art. Performs initialization of various flags and registers, and executes necessary failure diagnosis processing.

According to the third aspect of the present invention, it is possible to diagnose each of the two clock supply systems each time the power is turned on, thereby significantly improving the reliability of the microcomputer device. it can.

According to a fourth aspect of the present invention, in the microcomputer device according to the first or second aspect, the diagnostic processing is executed in a state in which an interrupt to the CPU is disabled. It is in.

According to the present invention, the above-described diagnostic processing is executed in a state where interruption to the CPU is prohibited.

Here, such prohibition of the interrupt processing will be performed by inserting an interrupt prohibition instruction and an interrupt permission instruction before and after the diagnostic processing.

According to the fourth aspect of the present invention, since no other interrupt enters during the software timer processing, the accuracy of the measurement time measured by the software timer processing is guaranteed. Become.

According to a fifth aspect of the present invention, the diagnostic processing is performed in a state where the fastest clock is supplied to the timer circuit via the second clock supply system. A microcomputer device according to claim 1 or claim 2.

According to the fifth aspect of the present invention, the above-described diagnostic processing is performed in a state where the fastest clock is supplied to the external timer circuit.

Here, "the fastest clock" means that in this type of clock supply system, a prescaler, a selector, etc. are usually inserted, and one of a plurality of clocks having different speeds can be arbitrarily selected. This is in consideration of the fact that it can be selected under the control of the CPU.

According to the fifth aspect of the present invention, since the clocking operation in the timer circuit is performed using the fastest clock, a highly reliable failure diagnosis is performed using a highly accurate measurement time. It becomes possible.

[0031]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

As is well known, a microcomputer of this type includes a CPU for executing a program, a ROM for storing the program, a RAM used as a working area and the like, and an interface circuit for input / output. And an external timer circuit for executing a timer process. The CPU sequentially reads instructions from the ROM in accordance with a program counter,
Generally, this is executed using an ALU and using a working area in a RAM, and the final execution result is output to the outside via an interface circuit. The basic operation of such a microcomputer is widely known in various documents, and therefore, description thereof is omitted. Hereinafter, the configuration of a clock supply system, the configuration of a timer circuit, and the system program which are the main parts of the present invention The configuration will be mainly described.

FIG. 1 shows the configuration of the clock supply system of the microcomputer device according to the present invention. The microcomputer device shown in the figure is a so-called one-chip microcomputer or the like. Although not shown, the microcomputer device is configured by integrating a CPU, a ROM, a RAM, and peripheral hardware on a single chip. Is supplied from an externally provided crystal oscillation circuit or the like.

That is, a clock source 2 composed of a crystal oscillation circuit is provided outside the one-chip microcomputer 1.
The clock signal output from the clock source 2 is supplied to the one-chip microcomputer 1 and then to the main system clock generating circuit 3.

The main system clock generating circuit 3
After appropriately adjusting the frequency of the clock supplied from the clock source 2, the clock signal fx is output. After this clock signal fx is further divided into two systems, one is supplied to an input terminal I1 of a selector 4 provided at the subsequent stage, and the other is divided by two by a frequency dividing circuit 5, and the clock signal fx / 2, the other input terminal I2 of the selector 4
Supplied to.

The selector 4 is configured to perform switching control in accordance with a command from a CPU (not shown). Therefore, the output terminal O of the selector 4 has two input terminals I
The clock signal supplied to one of I1, I2 is output as the clock signal fxx. This clock signal f
xx is further branched into two systems, one of which is a CPU
To the first clock supply system A leading to the peripheral hardware and to the second clock supply system B leading to the peripheral hardware.

The first clock supply system A, based on the clock signal fxx, has four clock signals fxx / 2 ⁴ , fxx / 2 ³ , fxx / 2 ² , fxx with different division ratios.
/ 2, and the prescaler 6
And a selector 7 for selecting one of the clock signals fxx output from the selector 4 and the four clock signals generated by the selector 4. That is, as is well known, the prescaler 6 is formed by cascade-connecting T-type flip-flops, and has output terminals O1 to O4.
, The output of each subordinate stage is output to the outside in parallel.
The output signals from the output terminals O1 to O4 of the prescaler 6 are supplied to the input terminals I1 to I4 of the selector 7, and the clock signal fxx output from the output terminal O of the selector 4 is also supplied to the input terminal I5 of the selector 7. Is supplied. The selector 7 is configured to perform switching control according to a command from a CPU (not shown), similarly to the selector 4 described above, and any one of the clock signals supplied from its output terminal O to the input terminals I1 to I5. Is output as a CPU clock fcpu, and this clock signal fcpu is supplied as an operating clock to a clock input terminal of a CPU (not shown).

On the other hand, the second clock supply system B includes a prescaler 8 having a configuration similar to that of the prescaler 6 described above. A plurality of clock signals obtained from the prescaler 8 are supplied to a timer circuit. To peripheral hardware, including: Although not shown here, a selector having the same configuration as the selector 7 described above is arranged in front of each timer circuit and the like constituting the peripheral hardware.
According to a command from the PU, a clock signal for a clock-using device such as a timer circuit can be selected from a plurality of types of clock signals prepared in advance. That is, in the program to be executed by the CPU, by selecting a clock using a predetermined instruction word, the clock used by the timer circuit and the clock-using device can be arbitrarily switched to, for example, high speed, medium speed, or low speed. Has been made possible.

Next, a configuration of a timer interrupt circuit including a timer circuit which is a main part of the present invention is shown in a logic symbol diagram of FIG. This timer interrupt circuit is composed of two systems of timer interrupt circuits having the same configuration.

That is, the first timer interrupt circuit performs a time measurement operation with reference to the count clock φ1 and compares the measured time with a timer circuit TM1 and a timer circuit TM1. A compare register CR1 in which a target time to be written can be written via a program, is set to "1" when the measured time of the timer circuit TM1 matches the measured target time of the compare register CR1, and its contents are programmed. , An interrupt mask flag MK1 that can be set to “1” or “0” by a program, and an interrupt mask flag MK1 are set to “1”. At this time, an interrupt prohibition gate G11 for prohibiting the output of the content of the interrupt flag IF1 from being output.
And an interrupt enable gate G12 controlled by the output of an interrupt enable flag IE that can be set to "1" or "0" by a program.

Similarly, the second timer interrupt circuit performs a time measurement operation on the basis of the count clock φ2, and can refer to the measured time by a program. A compare register CR2 in which a measurement target time to be compared can be written by a program, is set when the measurement time of the timer circuit TM2 coincides with the measurement target time of the compare register CR2, and its contents are stored in the program. Flag IF2 that can be referred to as “1” by the program
Alternatively, an interrupt mask flag MK2 that can be set to “0” and a signal for prohibiting output of the contents of the interrupt flag IF2 when the interrupt mask flag MK2 is set to “1”. It comprises an interrupt prohibition gate G21 and an interrupt permission gate G22 controlled by the above-described interrupt enable flag IE. The signals output from the interrupt permission gates G12 and G22 are
M1 match interrupt signal S1, timer TM2 match interrupt signal S2
Is supplied to an interrupt input unit (not shown) of the CPU.
As a result, a so-called timer interrupt occurs during execution of the program.

In the circuit described above, the count clocks φ1 and φ2 correspond to one of a plurality of clock signals supplied via the second clock supply system B described with reference to FIG.
That is, as described above, by using a predetermined clock selection instruction in a program, it is possible to arbitrarily switch between a high-speed clock, a medium-speed clock, a low-speed clock, and the like. In the diagnostic processing of the present invention described later, the fastest clock is selected as the count clock φ1.

Next, the configuration of the diagnostic processing according to the present invention will be sequentially and systematically described with reference to the flowchart of FIG.
The program shown in the figure is executed as initialization processing immediately after the power supply is introduced.

That is, when the process is started in the figure, first, an interrupt prohibition process is executed (step 20).
1). In this interrupt prohibition process, the interrupt enable flags IE shown in FIG. 2 are reset to "0" to close the interrupt permission gates G12 and G22, and all other interrupt circuits other than the timer interrupt. In the same way, the corresponding gate is closed so as not to interrupt.

Next, when the timer TM1 clock setting process is executed (step 202), the highest-speed clock is selected as the count clock φ1 by controlling the above-described selector (not shown) through a program. Here, a clock of 0.4 μs is selected as such a fastest clock.

Next, when the timer TM1 start process is executed (step 203), a timer start / stop flag (not shown) is set to "1",
Activation of the timer circuit TM1 is performed. This type of timer start / stop flag is widely used in this type of microcomputer device, as is well known to those skilled in the art.
When this flag is reset to "0" in the program, the timer circuit TM1 is stopped in a cleared state, and when set to "1", the measuring operation is started from the set point.

Next, when the soft timer process is executed (step 204), a predetermined target time (here, 1.
7234 ms). The details of this type of software timer processing are widely known to those skilled in the art in various documents and the like, that is, the target time is measured by repeatedly executing a fixed program in which the cycle execution time is defined. Things. At this time, a clock of 0.2 μs is used as the operation clock of the CPU.

Next, when reading processing of the timer TM1 measurement value is executed (step 205), the elapsed time measured by the timer circuit TM1 is read, and the elapsed time is stored in the register tm1. That is,
As described above, the measurement value of the timer circuit TM1 can be arbitrarily read by using a predetermined instruction word in the program, and the elapsed time thus read is stored in a RAM (not shown). It is stored in a register tm1 provided in the working area.

Next, when the stop processing of the timer TM1 is executed (step 206), the start / stop flag described above is reset to "0", whereby the measuring operation of the timer circuit TM1 is reset to zero. Will be stopped.

Next, when the measurement time comparison process is executed (step 207), the measurement time measured by the hardware timer process using the timer circuit TM1 and the measurement time measured by the software timer process of step 204 are executed. Collation with time is performed with a predetermined tolerance. here,
1.7 which is the target time in software timer processing
234 ms is measured with a clock of 0.4 μs,
438.5 clocks (1.7234 ms / 0.4μ)
s). Therefore, the above-described measurement time comparison is performed by checking whether the measurement time measured by the timer circuit TM1 falls between the predetermined lower limit 10CBh (= 4299 clocks) and the predetermined upper limit 10DFh (= 4319 clocks). It is performed by determining whether or not it is.

Here, if it is determined that the measurement time tm1 measured by the hardware timer process falls within the predetermined upper and lower limit values (step 207 YES), an interrupt permission process is executed (step 208). The prohibition of not only the timer interrupt process but also all other interrupt processes is released, the diagnostic process is terminated, and a shift to the original main routine process (control process, etc.) is performed. On the other hand, if it is determined that the measurement time tm1 measured by the hardware timer process is out of the predetermined upper and lower limit values (NO in step 207), a predetermined abnormal time process is executed (step 209). That fact is notified to the outside, and necessary safety processing and the like are executed.

As described above, according to the above-described embodiment, the timer circuit activation process (step 203) for activating the timer circuit TM1 to perform the clocking operation is performed.
A software timer process (step 204) that is started almost simultaneously with the start of M1 and counts a predetermined target time;
In response to the completion of the timekeeping operation in the software timer process, the elapsed time of the timer circuit TM1 is read (step 205), and this is compared with the target time (1.7234 ms) of the software timer circuit (step 207). Therefore, in the first clock supply system A for supplying a clock to the CPU or the second clock supply system B for supplying a clock to peripheral hardware including the timer circuit TM1, a prescaler is provided. In the case where the speed of the operation clock is deviated due to the occurrence of a bit stuck failure or the like in the selector or the selector, such an abnormality is accurately detected by a verification mismatch (step 207). Can be diagnosed.

In the above embodiment, an interrupt prohibition process is performed before and after the diagnostic process (step 201).
And an interrupt permitting process (step 208) to prevent any interruption during the software timer process, so that the accuracy of the measurement time measured by the software timer process is reliably guaranteed. And the reliability of the diagnosis can be assured.

Further, in the above embodiment, since the highest clock (0.4 μs) is used as the clock used in the hardware timer processing, the measurement accuracy in the hardware timer processing is high, and This realizes a more reliable diagnosis process.

In the above embodiment, in response to the completion of the measurement of the predetermined time (1.7234 ms) in the software timer process (step 204), the elapsed time in the hardware timer process is read. On the other hand, a timer interrupt is generated in response to completion of measurement of a predetermined time in the hardware timer process, and the elapsed time of the software timer process is included in the interrupt process. It is considered that a similar abnormality diagnosis can be performed by reading both and then comparing them.

[0056]

As is apparent from the above description, according to the present invention, the clock supplied to the CPU has an irregular speed or the clock supplied to the peripheral hardware has an irregular speed. In such a case, there is an effect that a microcomputer device having a function of accurately diagnosing this can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a configuration of a clock supply system in a microcomputer device according to the present invention.

FIG. 2 is a logic symbol diagram showing a configuration of a timer interrupt circuit including a timer circuit which is a main part of the present invention.

FIG. 3 is a flowchart showing details of a diagnosis process according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 One-chip microcomputer 2 Clock source 3 Main system clock generation circuit 4 Selector 5 Divider circuit 6 Prescaler 7 Selector 8 Prescaler A 1st clock supply system B 2nd clock supply system TM1, TM2 Timer circuit CR1, CR2 Compare Register IF1, IF2 Interrupt flag MK1, MK2 Interrupt mask flag G11, G21 Interrupt inhibit gate G12, G22 Interrupt enable gate IE Interrupt enable flag

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirotaka Kojima 1-4-24 Shiromi, Chuo-ku, Osaka-shi, Osaka Within NEC Home Electronics Co., Ltd. No. 1 In Honda R & D Co., Ltd. (72) Inventor Tatsuo Hayashi Incorporated in Honda R & D Co., Ltd.

Claims (5)

[Claims] 1. A CPU for executing a program,
A timer circuit usable through the program; a first clock supply system for supplying a clock to the CPU; and a second clock supply system for supplying a clock to peripheral hardware including the timer circuit. A clock supply system, wherein a diagnostic process for diagnosing a state of the microcomputer device is incorporated in a system program of the microcomputer device. A measurement time measured by executing a predetermined program in the CPU with reference to a clock supplied through the first clock supply system, and a clock supplied through the second clock supply system. The measured time measured by the timer circuit is collated as a reference, and if there is an abnormality based on the collation result. The includes determining process, the microcomputer system, characterized in that. 2. A CPU for executing a program,
A timer circuit available through the program, a first clock supply system for supplying a clock to the CPU, and a second clock supply system for supplying a clock to the timer circuit. In the microcomputer device, a diagnostic process for diagnosing a state of the microcomputer device is incorporated in a system program of the microcomputer device, and the diagnostic process activates the timer circuit. A timer circuit starting process for causing the timer circuit to perform a time counting operation; a software timer process being started almost simultaneously with the start of the timer circuit to count a predetermined target time; and a time counting operation being completed by the software timer process. In response, the elapsed time of the timer circuit is read, and is read by the software timer. A matching process for matching time, based on the collation result in the matching process, and a determination processing of determining whether there is an abnormality, the microcomputer system, characterized in that. 3. The microcomputer device according to claim 1, wherein the diagnosis process is performed by an initialization process in a system program. 4. The microcomputer device according to claim 1, wherein the diagnosis process is executed in a state in which an interrupt to the CPU is disabled. 5. The diagnosis process according to claim 1, wherein the diagnosis process is performed in a state where the fastest clock is supplied to the timer circuit via the second clock supply system. The microcomputer device according to claim 1.