JPS6257052A - ト−ラス結合型モジユ−ル配列実装方式 - Google Patents

ト−ラス結合型モジユ−ル配列実装方式

Info

Publication number
JPS6257052A
JPS6257052A JP60196024A JP19602485A JPS6257052A JP S6257052 A JPS6257052 A JP S6257052A JP 60196024 A JP60196024 A JP 60196024A JP 19602485 A JP19602485 A JP 19602485A JP S6257052 A JPS6257052 A JP S6257052A
Authority
JP
Japan
Prior art keywords
module
row
terminal
odd
numbered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60196024A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0241779B2 (2
Inventor
Takumi Watanabe
渡辺　琢美
Toshio Kondo
利夫 近藤
Toshio Tsuchiya
敏雄 土屋
Kichi Sugiyama
杉山　吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60196024A priority Critical patent/JPS6257052A/ja
Publication of JPS6257052A publication Critical patent/JPS6257052A/ja
Publication of JPH0241779B2 publication Critical patent/JPH0241779B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
JP60196024A 1985-09-06 1985-09-06 ト−ラス結合型モジユ−ル配列実装方式 Granted JPS6257052A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60196024A JPS6257052A (ja) 1985-09-06 1985-09-06 ト−ラス結合型モジユ−ル配列実装方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60196024A JPS6257052A (ja) 1985-09-06 1985-09-06 ト−ラス結合型モジユ−ル配列実装方式

Publications (2)

Publication Number Publication Date
JPS6257052A true JPS6257052A (ja) 1987-03-12
JPH0241779B2 JPH0241779B2 (2) 1990-09-19

Family

ID=16350949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60196024A Granted JPS6257052A (ja) 1985-09-06 1985-09-06 ト−ラス結合型モジユ−ル配列実装方式

Country Status (1)

Country Link
JP (1) JPS6257052A (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511887A (ja) * 1990-12-31 1993-01-22 American Teleph & Telegr Co <Att> マルチプロセツサボードスタツク及びそのモジユール配置方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511887A (ja) * 1990-12-31 1993-01-22 American Teleph & Telegr Co <Att> マルチプロセツサボードスタツク及びそのモジユール配置方法

Also Published As

Publication number Publication date
JPH0241779B2 (2) 1990-09-19

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