JPS625723U - - Google Patents
Info
- Publication number
- JPS625723U JPS625723U JP9704185U JP9704185U JPS625723U JP S625723 U JPS625723 U JP S625723U JP 9704185 U JP9704185 U JP 9704185U JP 9704185 U JP9704185 U JP 9704185U JP S625723 U JPS625723 U JP S625723U
- Authority
- JP
- Japan
- Prior art keywords
- aft
- output
- circuit
- voltage
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000005236 sound signal Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第１図は本考案の実施例によるＡＦＴオン、オ
フ回路、第２図はテレビ電波をビデオ信号とオー
デイオ信号に変換する回路のブロツク図、第３図
は従来のＡＦＴオン、オフ回路、第４図は従来回
路によるＡＦＴ電圧とドレイン端に出力される電
圧の関係図、第５図はＦＥＴのゲート、ソース間
電圧ＶＧＳとドレイン電流ＩＤの関係をあらわし
た図、第６図は本考案実施例によるＡＦＴ電圧と
ドレイン端に出力される電圧の関係図である。
１９……ＦＥＴ、２１……トランジスタ、２２
……ＡＦＴスイツチ、２３，２４……ダイオード
。
Figure 1 shows an AFT on/off circuit according to an embodiment of the present invention, Figure 2 is a block diagram of a circuit that converts television waves into video and audio signals, and Figure 3 shows a conventional AFT on/off circuit. The figure is a diagram showing the relationship between the AFT voltage and the voltage output to the drain end in a conventional circuit, Figure 5 is a diagram showing the relationship between the FET gate and source voltage VGS and the drain current ID, and Figure 6 is an example of the present invention. FIG. 2 is a diagram showing the relationship between the AFT voltage and the voltage output to the drain terminal. 19...FET, 21...Transistor, 22
...AFT switch, 23, 24...diode.
Claims (1)
をゲート端に印加する制御電圧によつてドレイン
端を出力および非出力に切換えるＡＦＴオン、オ
フ回路において、前記ＡＦＴ電圧を少くとも２個
のダイオードを極性を逆方向に並列接続した並列
接続体を介して前記ＦＥＴのソース端に入力した
ことを特徴とするＡＦＴオン、オフ回路。 In an AFT on/off circuit in which the AFT voltage input to the source end of a junction FET is switched between output and non-output at the drain end by a control voltage applied to the gate end, the AFT voltage is applied to at least two diodes for polarity. An AFT on/off circuit characterized in that the AFT is inputted to the source end of the FET via a parallel connection body in which the FETs are connected in parallel in opposite directions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9704185U JPH0332112Y2 (en) | 1985-06-26 | 1985-06-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9704185U JPH0332112Y2 (en) | 1985-06-26 | 1985-06-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS625723U true JPS625723U (en) | 1987-01-14 |
| JPH0332112Y2 JPH0332112Y2 (en) | 1991-07-08 |
Family
ID=30963549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9704185U Expired JPH0332112Y2 (en) | 1985-06-26 | 1985-06-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332112Y2 (en) |
-
1985
- 1985-06-26 JP JP9704185U patent/JPH0332112Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0332112Y2 (en) | 1991-07-08 |