JPS6355178U - - Google Patents
Info
- Publication number
- JPS6355178U JPS6355178U JP14971286U JP14971286U JPS6355178U JP S6355178 U JPS6355178 U JP S6355178U JP 14971286 U JP14971286 U JP 14971286U JP 14971286 U JP14971286 U JP 14971286U JP S6355178 U JPS6355178 U JP S6355178U
- Authority
- JP
- Japan
- Prior art keywords
- source
- circuit
- gate
- common
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Amplifiers (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案回路の一例を示す電気的接続図
、第２図はＦＥＴのゲート・ソース間電圧とドレ
イン電流との関係を示す線図、第３図は第１図に
おいてスイツチＳ１をオンとした後の容量Ｃｓの
両端電圧Ｖｏの変化を示す線図、第４図はサンプ
リング・ヘツドの入力回路の基本的な接続図、第
５図は第４図におけるスイツチ素子Ｓ１の構成接
続図である。
Ｓ１，Ｓ２…スイツチ、Ｑ１，Ｑ２…ＦＥＴ、
Ｒｓ…抵抗、Ｃｓ，Ｃｓｔ…コンデンサ、ＳＴ…
ストレツチヤー回路。
Fig. 1 is an electrical connection diagram showing an example of the circuit of the present invention, Fig. 2 is a diagram showing the relationship between the gate-source voltage and drain current of the FET, and Fig. 3 is a diagram showing the relationship between the gate and source voltage of the FET and the drain current. Figure 4 is a basic connection diagram of the input circuit of the sampling head, and Figure 5 is a diagram showing the configuration and connection of switch element S1 in Figure 4. be. S1, S2...Switch, Q1, Q2...FET,
Rs...resistance, Cs, Cst...capacitor, ST...
Stretcher circuit.
Claims (1)
サンプリングした信号を入力する２個のＦＥＴで
構成されたソース・フオロワ回路とからなるサン
プリング・ヘツドの入力回路において、前記サン
プリングした信号を入力するＦＥＴのゲートとコ
モンとの間に抵抗Ｒｓを接続すると共にこのＦＥ
Ｔのゲートとソースとの間及びソースとコモンと
の間にコンデンサを接続し、前記ソース・フオロ
ワの出力電圧をストレツチヤー回路を介して得る
ようにしたことを特徴とするサンプリング・ヘツ
ドの入力回路。 In the input circuit of the sampling head, which consists of a switching element and a source follower circuit composed of two FETs that input the signal sampled by the switching element, the gate of the FET that inputs the sampled signal and the common A resistor Rs is connected between this FE
1. An input circuit for a sampling head, characterized in that a capacitor is connected between the gate and source of T and between the source and common, and the output voltage of the source follower is obtained via a stretcher circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14971286U JPS6355178U (en) | 1986-09-30 | 1986-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14971286U JPS6355178U (en) | 1986-09-30 | 1986-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6355178U true JPS6355178U (en) | 1988-04-13 |
Family
ID=31065182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14971286U Pending JPS6355178U (en) | 1986-09-30 | 1986-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6355178U (en) |
-
1986
- 1986-09-30 JP JP14971286U patent/JPS6355178U/ja active Pending