JPS6258231B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power line carrier control device that superimposes a carrier wave on a power line and controls and monitors a receiver side.

The power line transport system uses a general power line 1 as a signal line to perform remote control and monitoring, and a model diagram of the conventional system is shown in FIG. Thus, in FIG. 1, transmitters 2 ₁ , 2 ₂ are connected to power line 1.
and receivers 3 ₁ and 3 ₂ are connected, and both receivers 3
Loads 9 ₁ and 9 ₂ are connected to ₁ and 3 ₂ .
For example, when a signal is transmitted from the transmitter ₂₁ , the receiver ₃₁ receives the signal and operates a relay contact or the like to turn on/off the load ₉₁ . That is, in this example, the transmitter ₂₁ controls the receiver ₃₁ , and the transmitter ₂₂ controls the receiver ₃₂ , respectively. Considering the _case where _a plurality of sets of transceivers _{2 1} . An example of a signal format using this is shown in FIG. 2. The 4-bit address code in the center of FIG. In addition, the first 1 bit S in the figure is a start mark, which is used to synchronize the transmitter/receivers ₂₁ ... ₃₁ ..., and the 4 bits of the mode code indicate the content of the signal to be controlled. For example, set it to 0000 for on, 0001 for off, and 1000 for dimming. Furthermore, the last 4 bits of the control code are used to transmit additional information, such as the dimming level during dimming.

Figure 3a shows an example of the content (structure) of this 1 bit, where the transmission signal is sent in synchronization with the power frequency of power line 1, and 1 bit is transmitted during a half wave of the power supply waveform. It is used to transmit information, and a zero-cross pulse as shown in FIG. 3b is extracted from the power supply waveform and used as a synchronization signal. FIG. 3A shows the waveform of the power line 1 on which the transmission signal is actually carried, and is a form in which the carrier signal B is superimposed on the AC waveform A of the power source. In addition, in this Figure 3, the half-wave section is divided into four, and the four pieces of data represent a start mark when 0101, data "0" when 0100, and data "1" when 0111, to improve reliability. This is a 1-bit signal format.

FIG. 4 shows the input/output in normal use. An on switch 10 and an off switch 11, an up switch, a down switch, etc. are connected to the transmitter 2 as push-on type switches, and the on switch 12 of the receiver 3 is connected to the transmitter 2 as a push-on type switch. /off, or change the position of the triact trigger pulse for dimming. Also, in this circuit shown in Figure 4, relay 1
2 shows an example in which a two-winding latching type is used. FIG. 5 shows a timing chart during operation of the circuit in FIG.
It outputs an SCR trigger signal for the relay 12, such as the one shown in FIG.
d in the figure is a transmission end signal.

FIG. 6 shows a block diagram of the main circuits of the transceivers 2 and 3.
The transmitter/receiver section is made of a microcomputer, LSI, etc., and since the transmitter 2 monitors the signal on the power line 1 and transmits only when there is no signal, it has a transmitter/receiver function. Both have a common circuit configuration. The functions of each part will be briefly explained below. In the circuit shown in FIG. 6, the modem section 1
3 converts the carrier signal on the power line 1 into a logic level signal, modulates the transmission data carrier wave, and superimposes it on the power line 1. The CK generating section 14 detects the zero crossing of the power supply waveform and creates clock pulses necessary for each section based on the generated zero crossing pulse. The received signal verification section 15 classifies the received modulated signal into data "1", "0", start mark, etc. The reception shift register 16 converts the 1/0 data from the reception number verification unit 15 into parallel data, and decomposes it into a mode code, an address code, and a control code. The address verification section 17 verifies whether the address code of the received number matches the own address. The mode verification section 18 verifies the mode code of the received issue. The relay drive trial trigger unit 19 outputs a drive pulse for the relay 12 to the relay drive output according to the content of the mode code, and outputs a trigger pulse for phase control to the dimming trial trigger output according to the control code. Output. When receiving the dimming mode, the dimming data reproducing unit 20 reads the contents of the control code and determines the position of the triact trigger pulse. Next, the key input section 21 receives key inputs such as on/off operations, and inputs transmission data such as address data and dimming data, and converts it into a logic signal. Transmission data creation section 22
creates parallel data to be transmitted based on the data input from the key input section 21 and the transmission/reception setting status.
The start pulse generator 23 generates a start pulse to start the transmission operation when a key is input. The transmission shift register 24 converts parallel data for transmission into serial data, and the transmission signal generation section 25 outputs the serial data from the transmission shift register 24 one bit at a time and outputs the final input signal to the modulation/demodulation section 13. It is designed to output a transmission end signal at the end of each transmission signal.
The error detection unit 26 performs a transmitting/receiving operation when receiving an incorrect mode code or a code from an address other than its own, or when the transmitted number and the received number that received the transmitted number are different during transmission. The busy detection unit 27 stops the signal transmission and waits in the original state, and if there is already a signal or noise on the power line 1 when attempting to transmit, the busy detection unit 27 temporarily waits for signal transmission, and then transmits again after a certain period of time. Outputs a signal to start. The transmission/reception timing control section 28 controls the transmission/reception timing and operates each section according to a clock signal.Furthermore, when the above-mentioned error signal occurs,
It stops transmission, waits for a certain period of time, and then retransmits it. Thus, the power line carrier control device comprising the transceiver with the above configuration has the following functions. That is, according to the mode code, receiver 3 is connected to relay 1.
2 can be turned on and off, and the receiver 3 can adjust the light according to the signal (control code) from the transmitter 2. Furthermore, if an error occurs during transmission, it can control retransmission from the beginning. It turns out. Furthermore, the signal is transmitted only when no other signal is on the power line 1, which is a signal transmission line.

In a power line carrier control device using a circuit as shown in FIG. Only signals can be sent, and the system using the conventional example shown in Figure 6 can only control one load at a time, so the line utilization efficiency is low when considering the number of controlled loads, and if multiple loads are controlled. In this case, there is a problem in that the number of addresses must be used to transmit and control signals at different times, and the number of addresses is limited by the number of bits in the address code, so the maximum number of loads is also not small. There is a problem. In addition, when not only controlling but also monitoring the load status, in order to transmit the monitoring signal,
Furthermore, an address will be added, and FIG. 7 is a model diagram of one control and one monitoring in the conventional example, and two addresses are required for controlling and monitoring a single load.
One address is required. FIG. 8 shows a block diagram of a circuit in which a 4-bit bidirectional transmission function is added to the circuit shown in FIG. The circuit of FIG. 8 differs from the circuit of FIG. 6 in that the transmitting section has control data input, a control data output section 29 is provided from which 4-bit parallel output is possible, and the control data output section 2
9 contains the output of the mode verification section 18. In the figure, 30 is a mode data output section, 2
1' is a data input section. FIG. 9a shows an example of the circuit near the control data output section 29 that outputs 4 bits of control data of the receiving section, and FIG. 9b shows an example of the circuit near the control data and mode data input section of the transmitting section. . First, the circuit shown in FIG. 9 will be explained. The transmission signal becomes a 1/0 signal and is input to the reception shift register 16 in FIG. 9a in synchronization with the zero-cross signal of the power supply. Therefore, when the reception of the signals is completed, all the received signals are lined up in the reception shift register 16.
Here, the control code is placed in Q ₁ to _{Q 4} of the receiving shift register 16, the address code is placed in Q ₅ to Q ₈ , and
The mode codes are arranged in Q ₉ to Q ₁₂ , respectively.
Here, the address code is verified by the address verification section 17 to see if it matches the address of the user. The control code is input to a control data output section 29 consisting of a 4-bit latch and is latched. However, as the CK of this latch, the data latch pulse output from the transmission/reception timing control section 28 and the mode code output from the mode verification section 18 are ANDed. Here, the data latch pulse is output after signal reception is completed, and Q ₁ to _{Q 4}
Occurs after the control code is lined up. In addition, when the data latch mode changeover switch 31 is set to the upper side, when it is "000X" (X can be anything, in order from Q ₁₂ ), the control code is latched to the control data output section 29, and the changeover switch 31 is turned on as shown in the figure. When pushed down, it latches in mode “0100”.

Next is the transmitting section shown in figure b. Here, after inputting 12-bit parallel data of mode, address, and control into the transmitting shift register 24, it is converted into serial data in synchronization with the zero-cross signal (clock) and sent out. It can be done. Mode data input terminal P ₉ ~
The data latch mode changeover switch 32 connected to the input of the second bit from the top of _P12 allows the mode to be switched between "000X" and "010X" for transmission.

Thus, the transceivers 2 and 3 with these circuits added
is connected to the power line 1, which is a signal line, as shown in FIG. Here, 2 is a transmitter, 3 is a receiver,
9 ₁ to 9 ₄ are loads to be controlled. The system shown in FIG. 10 is a 4-control, 4-monitor system, in which a control signal, that is, a control signal, is transmitted from the transmitter 2, and the receiver 3 receives this.
Controls loads ₉₁ to ₉₄ . On the other hand, the receiver side 3 side monitors the states of the loads ₉₁ to ₉₄ using sensors, etc.
This is sent back to the transmitter 2 as a monitoring signal, and the transmitter 2 outputs and displays this monitoring status. Here, when the transmitter 2 side transmits a control signal, it sets the mode code to "0000" and transmits the control content on the control code part. In addition, on the receiver 3 side, if the control code is set to be latched when the mode code is "000X", the control signal will appear in the 4-bit output of the control data of the receiver 3, and the load 9 ₁ to 9 ₄
control. Furthermore, a monitoring signal from the monitoring performed by the receiver 3 is inputted from the monitoring input of the receiver 2. This has a mode code of "0100" and a monitoring signal is placed on the control code part, and the address code is transmitted from the transmitter 2 to the receiver 3 using the same address. If the receiving part of the transmitter 2 is set to be latched as a control data output when the mode code is "010X", a monitoring signal will be output to the transmitter 2. Here, even if transmitter 2 transmits, the receiving section of transmitter 2 does not latch the control data part of mode "000X", so transmitter 2 always outputs a monitoring signal, and similarly, receiver 3 outputs a monitoring signal. always outputs only control data.

Since the circuits in FIGS. 8 to 10 are configured as described above, they are not only able to control multiple loads 9 ₁ and 9 ₂ simultaneously, but also control signals and monitoring signals at the same address. In addition to being able to transmit signals without confusion, the same conventional signal format can be used for both control and monitoring, eliminating the need to lose traditional functions or require changes to peripheral circuits. This also improves the efficiency of using the line as a whole.

FIG. 11 shows a circuit diagram of a conventional example of a receiver 3 that transmits monitoring data to the transmitter 2 when the monitoring input to the receiver 3 changes by one bit. In the conventional circuit shown in FIG. 11, the outputs of change detection circuits ₄₁ to ₄₄ , which detect whether or not there is a change in each bit of the monitoring input, are summarized by an OR circuit 33.
When the output of this OR circuit 33 becomes "H" level, the set input of RS type latch 7 composed of two NOR gates becomes "H" level, and the positive logic output of this latch 7 becomes "H". Receiver circuit R
The trigger input terminal, which operates at the rising edge of , becomes "H" level, and signal transmission begins. After this, a relay drive output is generated from the receiver circuit R and the latch 7 is
will be reset. Here, change detection circuit 4 ₁ to 4
₄ is configured as shown in FIG. 12, for example, in which the input signal is directly input to one side of the exclusive OR circuit 34, and the input signal is input to the other side through an integrating circuit consisting of resistors R ₁ , R ₂ and capacitor C. When an input signal is input and a change occurs in the input signal, an "H" output is obtained on the output line of the exclusive OR circuit 34.
The receiver signal R in the figure includes all the main circuit parts of the receiver 3, and includes all the main circuit parts of the receiver 3, and is
It includes all the circuit parts corresponding to the circuit parts shown in the figure.

Thus, in the conventional circuit shown in FIG. 11 as described above, signal transmission is performed as shown in FIG. 13b in response to a change in the monitoring input shown in FIG. In response to a change in the monitoring input shown in Figure 13a, a signal is immediately transmitted for each change in the monitoring input as shown in Figure 13b, but the monitoring shown in Figure 13a that occurs during signal transmission The problem with input changes is that they are ignored and changes in the monitored input are not transmitted to the transmitter 2.

The present invention has been provided in view of the above-mentioned points, and provides a power line carrier control device that is capable of reliably transmitting changes to a monitoring input to a transmitter without ignoring them. The purpose is to

An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 14 shows a circuit according to a first embodiment of the present invention, which is configured so that 4-bit monitoring data is input to the data input of the receiver circuit R via a monitoring data buffer 5. The configuration is such that changes in each bit of the data input of the receiver circuit R are detected by the (second) change detection circuits ₄₁ to ₄₄ , and the output of this latch 7 is input to the trigger input of the receiver circuit R. , is similar to the case of the conventional example shown in FIG. 11 described above. The monitoring data buffer 5 shown in FIG. 15 is constituted by a so-called FIFO buffer configured so that the data that enters first comes out first. In this embodiment, data is transmitted every 4 bits, and internally, a maximum of 4 bits is stored. ×16 data can be stored. To latch 4-bit input data, input a pulse to the SI terminal in Figure 15, and to output 4-bit data, input a pulse to the SO terminal. Furthermore, when the internal memory of this monitoring data buffer 5 [FIFO buffer] is full, the DIR terminal becomes “H” level and the DOR
The end becomes "H" level when data is entered into the internal memory of the monitoring data buffer 5. In short, the FIFO buffer is composed of a 4-bit x 16 memory, a shift register, etc., and operates as described above. In the embodiment shown in FIG. Insert it into the data input section of the device circuit R,
Data input D of monitoring data buffer 5
0 to D3, and the data outputs Q0 to Q3 of the monitoring data buffer 5 to the receiver circuit R.
has been entered into the data input. Further, first change detection circuits ₆₁ to ₆₄ are connected to each bit of the monitoring input, and the outputs of these first change detection circuits ₆₁ to ₆₄ are combined by an OR circuit 35, and the output is sent to the monitoring data buffer 5. is input to the shift-in input SI of the monitor, and if any one bit of the monitoring input changes,
The monitoring input data at that time is latched. In addition, the data out ready output DOR of the monitoring data buffer 5 and the transmission end signal output of the receiver circuit R are input to an AND circuit 36, and the output of this AND circuit 36 and the above DOR output via the rising edge detection circuit 40 are connected to an OR circuit. 37 are collectively input to the shift-out input SO, and when the DOR output rises, and when the DOR output is "H" and a transmission end signal is generated, the output of the monitoring data buffer 5 is input to the data of the receiver circuit R. It is set to be input into the input field.

Thus, in the embodiment circuit of FIG. 14, if even one bit of the four bits of monitoring input changes,
The output of the OR circuit 35 becomes "H", and the monitoring data buffer latches the monitoring input at this time. As a result, the DOR output of the monitoring data buffer 5 rises, so that the output of the OR circuit 37 becomes "H" and 4-bit data is outputted to the output of the monitoring data buffer 5. As a result, the output of the OR circuit 33 becomes "H" and the output of the latch 7 becomes "H", so that the receiver circuit R starts transmitting. Let us now consider the case where the 4-bit monitoring input changes while the receiver 3 is transmitting data to the transmitter. In the circuit of FIG. 14, the output of the OR circuit 35 becomes "H" every time the 4-bit monitoring input changes, so the 4-bit monitoring data is latched and the monitoring data buffer 5 is Memorized internally. The receiver 3 issues a transmission end signal every time it completes transmission, and reads out the data in the monitoring data buffer 5 using this signal. Then, start sending again,
This operation is repeated until the DOR terminal of the monitoring data buffer 5 becomes "L" level, that is, until the memory of the monitoring data buffer 5 becomes empty. In the above, 4 bits x 16 pieces of data can be stored in memory by using one monitoring data buffer 5, but it is clear that the above operation can also be performed using multiple monitoring data buffers 5. An example in which two monitoring data buffers 5 are used is shown in FIG. However, in the embodiment described above, when changes in the monitoring input occur frequently, even if changes in the 4-bit monitoring input occur within the signal transmission time, all 4-bit monitoring input This has the effect of making it possible to transmit changes in

FIG. 17 shows a configuration example of a second embodiment of the present invention, and in the circuit shown in FIG. 14, the monitoring data buffer 5 is
In the circuit shown in Fig. 17, data is output at the rising edge of the DOR terminal, but the clock input at the time of count up of the counter 8 that counts the clock input is outputted to the monitoring data buffer when the DOR terminal of the monitoring data buffer 5 is at high level. Data is output by inputting it to the shift out input SO of No. 5. In other words, in this embodiment, there is a counter 8 that counts the clock input, and an AND circuit 41 that ANDs the clock input and the output of the counter 8.
In addition to the AND circuit 36 and the OR circuit 37, an AND circuit 42 which performs an AND operation between the DOR output and the output of the AND circuit 41 is provided. Here counter 8
As the clock input, for example, a zero-cross pulse can be considered, whereby 4-bit data is read from the memory of the monitoring data buffer 5 and transmitted only during a fixed period having a predetermined time interval. Therefore, in the embodiment circuit of FIG. 17, when changes in the monitoring input occur frequently, transmission is not performed every time a change in the monitoring input occurs, but at every predetermined time interval when the counter 8 counts up. Since the 4-bit monitoring data is sent together, the line is completely empty, which means that the transmission and reception of other transmitters and receivers can be interrupted, so there is less chance of problems with signal transmission. It is. Furthermore, the transmitter that receives the monitoring data can process the monitoring data for each terminal at once, which simplifies the processing of the transmitter.

FIG. 18 shows a configuration example of a third embodiment of the present invention, and in this embodiment circuit, the monitoring data buffer 5 is
An OR gate 37 is connected to the SO terminal, and its inputs are the DIR terminal of the monitoring data buffer 5, the transmission end signal of the receiver circuit R, and the monitoring data buffer 5.
The output of the AND circuit 36 obtained by ANDing the DOR output of is connected. Therefore, in the circuit shown in FIG. 18, each time the monitoring input changes, it is latched into the monitoring data buffer 5, and when 4 bits x 16 of these inputs are accumulated, the DIR terminal becomes "H" and the data is transferred from the memory of the monitoring data buffer 5. is read out and sent to receiver 3.
starts sending. Note that the DIR terminal becomes "L" when the first data is output. When all the contents of the memory of the monitoring data buffer 5 are read out, the DOR terminal becomes "L", so the AND circuit 3
The output of 6 is always "L". In other words, when the 4-bit monitoring input changes 16 times, the receiver 3 starts transmitting and sends 4×16 pieces of data, and when this is finished, it stops transmitting.

Thus, in the circuit of the embodiment described above, when changes in the monitoring input occur frequently, the signal is transmitted every time 4 bits x 16 pieces of monitoring data are accumulated, so there is always an empty line, so that other can facilitate signal transmission between transmitters and receivers,
Furthermore, since the monitoring data can be processed together on the transmitter side, data processing at the transmitter becomes easier.

Since the present invention is configured as described above, when a change in the monitoring input occurs, it can always be reliably transmitted to the transmitter side without being ignored, and changes in the monitoring input occur frequently. It has the effect that no trouble occurs even in such cases.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a general power line carrier control device, Fig. 2 is a configuration diagram of the same transmission signal, Fig. 3 a and b are explanatory diagrams of the above transmission waveform, and Fig. 4 is the same transmitter as above. Explanatory diagram of control operation from to receiver, fifth
Figures a to d are timing charts similar to the above, Figure 6 is a block diagram of a conventional transmitter/receiver circuit, Figure 7 is a block diagram of a conventional example in which one transmitter/receiver is installed on each of the transmitter and receiver sides, and Figure 8 The figure is a block diagram of another conventional transmitter/receiver circuit, FIGS. 9a and 9b are circuit diagrams of the same receiving section and transmitting section, and FIG. 10 is a block diagram of yet another conventional example having a monitoring input return function. figure,
Figure 11 is a block diagram of the same receiver as above, Figure 12 is a change detection circuit diagram used in the circuit in Figure 11, and
Figures 3a and b are diagrams explaining the operation of the circuit in Figure 11, and Figure 14.
The figure is a block diagram of a receiver according to an embodiment of the present invention.
5 is an explanatory diagram of the monitoring data buffer used in the circuit of FIG. 14, FIG. 16 is a circuit diagram of another example of the same monitoring data buffer, FIG. 17 is a block diagram of a second embodiment of the present invention, and FIG. The figure is a block diagram of a third embodiment of the present invention, in which 1 is a power line, 2, 2
₁ , 2 ₂ ... are transmitters, 3, _{3 1} , 3 ₂ ... are receivers, 4 ₁ , 4 ₂ '... are second change detection circuits, 5 is a monitoring data buffer, 6 ₁ , 6 ₂ ... are first 7 is a latch, and 8 is a counter.

Claims (1)

[Claims] 1. Power line carrier control in which a transmitter and a receiver are connected to a power line, and a carrier signal synchronized with the power waveform is superimposed on the power line so that the transmitter controls and monitors the receiver. The device includes a first change detection circuit that detects a change in a monitoring input, latches the input data every time an output of the first change detection circuit occurs, and outputs the output when the internal memory becomes full. and a monitoring data buffer that sequentially outputs the contents of the memory using a read signal;
The circuit includes a second change detection circuit for detecting a change in the output of the monitoring data buffer, and a latch connected to the output of the second change detection circuit, and detects the input data every time a change in the monitoring input occurs. A power line transport control device characterized in that it latches into the monitoring data buffer and sequentially reads out the latched monitoring data using an appropriate read signal and transmits the signals. 2. The power line transport control device according to claim 1, wherein the latched monitoring data is sequentially read out and transmitted by a read signal generated every time signal transmission is completed. 3. A counter is provided which counts clock pulses and allows input of a read signal to the monitoring data buffer for a certain period of time, and inputs a read signal to the monitoring data buffer every certain period. The power line transport control device according to scope 1. 4 The monitoring data buffer is equipped with a function to output a signal indicating that data is stored in the internal memory and a signal indicating that the internal memory is full, so that when the internal memory is full, 2. The power line transport control device according to claim 1, wherein the power line transport control device is configured to generate a read signal.