JPS6258542B2 - - Google Patents

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Publication number
JPS6258542B2
JPS6258542B2 JP55173523A JP17352380A JPS6258542B2 JP S6258542 B2 JPS6258542 B2 JP S6258542B2 JP 55173523 A JP55173523 A JP 55173523A JP 17352380 A JP17352380 A JP 17352380A JP S6258542 B2 JPS6258542 B2 JP S6258542B2
Authority
JP
Japan
Prior art keywords
photoresist
metal film
heat treatment
minutes
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55173523A
Other languages
Japanese (ja)
Other versions
JPS5796551A (en
Inventor
Koichi Higuchi
Masaaki Oohira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP17352380A priority Critical patent/JPS5796551A/en
Publication of JPS5796551A publication Critical patent/JPS5796551A/en
Publication of JPS6258542B2 publication Critical patent/JPS6258542B2/ja
Granted legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法、特にリフトオ
フ法を利用した配線形成方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming wiring using a lift-off method.

従来より、リフトオフ法は半導体装置の電極配
線形成の為の一方法として利用されてきている。
最も一般的なリフトオフ法は第1図a乃至第1図
dに示す様なフオトレジストだけを用いたもので
ある。半導体基板11上にフオトレジスト層12
を形成し(第1図a)、選択的に露光・現象しフ
オトレジストパターン13を形成し(第1図
b)、配線となるべき金属層14を被着する(第
1図C)。しかる後有機溶剤で処理し、フオトレ
ジストパターン13及びその上に被着した金属層
14を除去し、所望の配線パターンを半導体基板
上に残す方法である(第1図d)。
Conventionally, the lift-off method has been used as a method for forming electrode wiring of semiconductor devices.
The most common lift-off method uses only a photoresist as shown in FIGS. 1a-1d. Photoresist layer 12 on semiconductor substrate 11
(FIG. 1A), selectively exposed and developed to form a photoresist pattern 13 (FIG. 1B), and a metal layer 14 to be used as wiring is deposited (FIG. 1C). This method is then treated with an organic solvent to remove the photoresist pattern 13 and the metal layer 14 deposited thereon, leaving a desired wiring pattern on the semiconductor substrate (FIG. 1d).

この方法では、配線となるべき金属層の厚さ
が、フオトレジストパターン13の側面で薄くな
つていることが要求される。従つて配線となるべ
き金属は、フオトレジスト側面での被着膜厚が、
平坦部と比して薄くなる蒸着で形成されるのが一
般的である。しかし、チタン,白金の様な高融点
金属あるいは容易に酸化されやすい金属を電極配
線として使用する場合には、蒸着法では半導体基
板と配線との密着強度が弱くなる。蒸着時の高真
空度維持が困難である等の欠点があり、スパツタ
リングでの膜形成をする必要がある。この場合フ
オトレジストを用いたリフトオフ法で配線形成し
ようとすると、フオトレジスト側面での膜厚が蒸
着の場合を比してかなり厚くなる為リフトオフ性
が非常に悪くなるという問題が出てくる。最悪の
場合には、第2図に示す様にフオトレジスト上の
金属膜14′が残り、配線間のシヨートをひき起
こすという問題も発生する。
This method requires that the thickness of the metal layer that is to become the wiring become thinner on the side surfaces of the photoresist pattern 13. Therefore, the thickness of the metal that will become the wiring on the side of the photoresist is
It is generally formed by vapor deposition, which makes it thinner than the flat part. However, when a high melting point metal such as titanium or platinum or a metal that is easily oxidized is used as the electrode wiring, the adhesion strength between the semiconductor substrate and the wiring becomes weak in the vapor deposition method. There are drawbacks such as difficulty in maintaining a high degree of vacuum during vapor deposition, and the film must be formed by sputtering. In this case, when attempting to form wiring by a lift-off method using a photoresist, a problem arises in that the film thickness on the side surfaces of the photoresist becomes considerably thicker than in the case of vapor deposition, resulting in very poor lift-off properties. In the worst case, as shown in FIG. 2, the metal film 14' on the photoresist remains, causing shorts between wiring lines.

従つて本発明の目的は、従来のフオトレジスト
のみを使用したリフトオフ法でありながら、スパ
ツタリングの場合にもリフトオフ性が容易であ
り、歩留りの高い電極配線形成方法を提供するこ
とにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for forming an electrode interconnection, which is a conventional lift-off method using only a photoresist, but which has easy lift-off properties even in the case of sputtering and has a high yield.

本発明の特徴は、半導体基板上に2ミクロン以
上の膜厚のフオトレジスト層を形成する工程と、
該フオトレジスト層を選択的に露光・現象し、フ
オトレジストパターンを形成する工程と、該フオ
トレジストパターンを含む前記半導体基板に第一
の熱処理を100℃〜130℃で5分〜30分間行なう工
程と、しかる後スパツタリングにより電極配線と
なるべき金属膜を被着する工程と、該金属膜を含
む基板に第二の熱処理を150℃〜250℃で20分〜60
分間行なう工程と、該基板をトリクレンで処理
し、不要部分の該金属膜及び該フオトレジストパ
ターンを除去し、電極配線のみを残す工程とを含
む半導体装置の製造方法にある。
The features of the present invention include a step of forming a photoresist layer with a thickness of 2 microns or more on a semiconductor substrate;
A step of selectively exposing and developing the photoresist layer to form a photoresist pattern, and a step of performing a first heat treatment on the semiconductor substrate including the photoresist pattern at 100° C. to 130° C. for 5 minutes to 30 minutes. After that, a process of depositing a metal film to become an electrode wiring by sputtering, and a second heat treatment on the substrate containing the metal film at 150°C to 250°C for 20 minutes to 60 minutes.
and a step of treating the substrate with trichlene to remove unnecessary portions of the metal film and the photoresist pattern, leaving only electrode wiring.

ここでフオトレジストの膜厚を2ミクミン以上
とした理由は次の通りである。通常スパツタリン
グにより被着する金属膜の望ましい膜厚は4000Å
以下であり、またこれが実際多用される膜厚でも
ある。この時第4図に示す様に、次に述べる第
一、第二の熱処理の最適条件下でリフトオフが容
易となるフオトレジスト膜厚は2.5μm以上を得
た。同図でのリフトオフ良品率とは、所望の配線
間での金属膜残りのないチツプのウエハー全体の
チツプに対する割合を示している。ただし膜厚
2.0〜2.5μmのものでもトリクレンによるスクラ
ブを数回くり返すことにより、良品率は100%を
得ることができ、従つて実用性を考慮し、この膜
厚を2.0μm以上とする必要がある。ここでスク
ラブとは基体をトリクレンで処理し基板表面全体
を機械的にこすることである。
The reason why the film thickness of the photoresist is set to be 2 micumins or more is as follows. The desired thickness of the metal film usually deposited by sputtering is 4000Å.
This is also the film thickness that is often used in practice. At this time, as shown in FIG. 4, a photoresist film thickness of 2.5 μm or more, which facilitates lift-off under the optimal conditions of the first and second heat treatments described below, was obtained. The lift-off non-defective rate in the figure indicates the ratio of chips with no remaining metal film between desired wirings to the total number of chips on the wafer. However, film thickness
Even with a thickness of 2.0 to 2.5 .mu.m, a 100% yield rate can be obtained by repeating scrubbing with trichlene several times. Therefore, in consideration of practicality, it is necessary to set the film thickness to 2.0 .mu.m or more. Here, scrubbing means treating the substrate with trichlene and mechanically scrubbing the entire surface of the substrate.

次に第一の熱処理条件は次の理由で定めた。 Next, the first heat treatment conditions were determined for the following reasons.

第5図に実験結果の一例を示す。一般の熱処理
条件150℃、60分では全てシヨート不良となる。
本発明の様に低温化したもの(例えば120℃の場
合を示す)では、5〜30分と時間を短かくしてリ
フトオフ良品率100%のものが得られた。なおこ
の場合、さらに時間を短かくしたものでは、逆に
良品率が低下し、しかもスクラブ回数と関係しな
い。この理由は、一般に金属膜スパツタリングの
前に行なう希弗酸処理により、フオトレジストパ
ターンが基板との密着不良で剥れ、その結果金属
配線のシヨート不良となることによるものと考え
られる。また第一の熱処理時間が短かいと、金属
膜の被着時にアウトガスにより、基板への密着強
度が低下するという問題も発生する。本発明で
は、この様に一般の熱処理条件ではなく、低温・
短時間化をとつている。又、第5図のような120
℃における傾向は100℃〜130℃の範囲でみとめら
れた。
FIG. 5 shows an example of the experimental results. Under the general heat treatment conditions of 150°C and 60 minutes, all shots were defective.
When the temperature was lowered as in the present invention (for example, the case of 120° C. is shown), a lift-off rate of 100% was obtained by shortening the time to 5 to 30 minutes. In this case, if the time is further shortened, the rate of non-defective products decreases, and it is not related to the number of times of scrubbing. The reason for this is thought to be that the dilute hydrofluoric acid treatment generally performed before metal film sputtering causes the photoresist pattern to peel due to poor adhesion to the substrate, resulting in poor shorting of the metal wiring. Furthermore, if the first heat treatment time is short, there is a problem that the adhesion strength to the substrate is reduced due to outgas during deposition of the metal film. In the present invention, instead of using general heat treatment conditions as described above, low temperature and
We are working to shorten the time. Also, 120 as shown in Figure 5
A trend in °C was observed in the range of 100°C to 130°C.

次に第二の熱処理条件は次の理由で定めた。 Next, the second heat treatment conditions were determined for the following reasons.

第6図に実験結果の一例を示す。上記膜厚およ
び第一の熱処理の最適条件を用い、かつ金属膜を
スパツタした試料で、200℃での熱処理時間とリ
フトオフ良品率の関係を第6図に示す。20分以上
の熱処理でリフトオフ性は良くなつた。60分より
長い時間では時間が長くなりすぎ実用的でない。
この第二の熱処理が低温の場合(130℃の例を示
す)には、リフトオフ性は極めて悪く、実験では
スクラブ回数を数回行なう場合も含めて150℃以
上の温度が必要と判明した。又、同図の200℃と
同様な傾向が150℃〜250℃でみとめられた。すな
わち、この温度範囲で20分〜60分熱処理するのが
好ましい。
FIG. 6 shows an example of the experimental results. FIG. 6 shows the relationship between the heat treatment time at 200° C. and the lift-off yield rate for a sample in which a metal film was sputtered using the film thickness and the optimum conditions for the first heat treatment described above. The lift-off property was improved by heat treatment for 20 minutes or more. A time longer than 60 minutes would be too long to be practical.
When this second heat treatment is performed at a low temperature (an example of 130°C is shown), the lift-off property is extremely poor, and experiments have shown that a temperature of 150°C or higher is required, including when scrubbing is performed several times. Moreover, the same tendency as at 200°C in the same figure was observed at 150°C to 250°C. That is, it is preferable to perform heat treatment in this temperature range for 20 minutes to 60 minutes.

第3図a乃至第3図eは本発明の好ましい一実
施例を示す。はじめに所望のP−N接合、絶縁
膜、コンタクト開孔部等の形成された半導体基板
31上にフオトレジスト層32を形成する(第1
図a)。フオトレジストとしてはOMR(東京応化
工業製,商品名)などであり、その厚さは約2μ
m以上が望ましい。しかる後フオトマスクを用
い、選択的に露光しつづけて現象処理を施すこと
でフオトレジストパターン33を形成する(第3
図b)。ついで第一の熱処理を行ないフオトレジ
ストの溶剤分を除去する。熱処理温度は100〜130
℃前後熱処理時間は5〜30分と熱処理条件は低温
で短時間が望ましい。次にフオトレジストパター
ンを含む基板上全面に所望の金属膜34をスパツ
タリングにより被着する(第3図c)。金属膜は
一層にかぎる事はなく、異なつた金属が二層、三
層と連続に被着されたものでもよい。金属膜の厚
さはリフトオフ性の容易さとのかねあいからフオ
トレジストの厚さが約2.5μmの時には4000Å以
下が望ましい。しかしそれ以上であつても、従来
法と比してリフトオフ性は非常に改善されたもの
が得られる。次にスパツタ膜の被着された基板に
第二の熱処理を行なう。熱処理の条件としては
150〜250℃,20〜60分が望ましく、この熱処理に
よつてフオトレジストパターンからの溶剤の飛び
出し、フオトレジストパターンの収縮がおこり、
フオトレジストパターン側面の金属膜に多数の亀
裂35が生じる。この亀裂の発生がリフトオフ性
を容易にする一因となる(第3図d)。次に60〜
80℃に加熱されたトリクレン中に基板全体を浸
す。これにより前記亀裂35からトリクレンがフ
オトレジストパターン33にしみ込み、フオトレ
ジストを膨潤させ、さらにリフトオフ性を容易に
させることができる。しかる後基板表面全体を機
械的にスクラブすることにより、フオトレジスト
パターン上面・側面の不要となる金属膜を除去
し、次いでフオトレジストはくり液で処理するこ
とによりフオトレジストを除去し、所望の電極配
線のみを残す(第3図e)。
Figures 3a to 3e illustrate a preferred embodiment of the invention. First, a photoresist layer 32 is formed on a semiconductor substrate 31 on which desired P-N junctions, insulating films, contact openings, etc. have been formed (first
Diagram a). The photoresist is OMR (manufactured by Tokyo Ohka Kogyo, trade name), and its thickness is approximately 2μ.
m or more is desirable. Thereafter, a photoresist pattern 33 is formed by selectively continuing exposure using a photomask and performing a phenomenon treatment.
Figure b). Next, a first heat treatment is performed to remove the solvent content of the photoresist. Heat treatment temperature is 100-130
It is preferable that the heat treatment time is 5 to 30 minutes, and that the heat treatment conditions are low temperature and short. Next, a desired metal film 34 is deposited on the entire surface of the substrate including the photoresist pattern by sputtering (FIG. 3c). The metal film is not limited to one layer, and may be one in which two or three layers of different metals are successively deposited. When the thickness of the photoresist is approximately 2.5 μm, the thickness of the metal film is desirably 4000 Å or less, considering the ease of lift-off. However, even if it is more than that, a product with significantly improved lift-off property compared to the conventional method can be obtained. Next, a second heat treatment is performed on the substrate on which the sputtered film has been deposited. The conditions for heat treatment are
Preferably, the temperature is 150 to 250°C for 20 to 60 minutes, and this heat treatment causes the solvent to jump out of the photoresist pattern, causing shrinkage of the photoresist pattern.
Many cracks 35 occur in the metal film on the side surface of the photoresist pattern. The occurrence of this crack is a factor that facilitates the lift-off property (Fig. 3d). Next 60~
Immerse the entire substrate in Triclean heated to 80 °C. As a result, trichlene penetrates into the photoresist pattern 33 through the cracks 35, swells the photoresist, and further facilitates lift-off properties. After that, the entire surface of the substrate is mechanically scrubbed to remove unnecessary metal films on the top and side surfaces of the photoresist pattern, and then the photoresist is removed by treatment with a photoresist stripping solution, and the desired electrodes are removed. Only the wiring remains (Figure 3e).

この実施例に示した電極配線形成方法は、従来
法と比し、熱処理を行なうという簡単な方法によ
りスパツタリングの様にフオトレジスト側面の金
属膜が厚い場合にも容易にリフトオフが可能とな
り、歩留りの高い電極配線を得ることができる。
Compared to conventional methods, the method for forming electrode wiring shown in this example allows for easy lift-off even when the metal film on the side surface of the photoresist is thick, as in the case of sputtering, due to the simple method of heat treatment, which improves yield. High electrode wiring can be obtained.

以上本発明について説明したが、本発明の技術
的範囲は上記実施例に限定されるものではない。
Although the present invention has been described above, the technical scope of the present invention is not limited to the above embodiments.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a乃至第1図d,第2図は従来の電極配
線形成方法による半導体装置の各工程における断
面図、第3図a乃至第3図eは本発明の半導体装
置の電極配線形成方法の一実施例を工程順に示す
断面図、第4図、第5図および第6図は本発明の
効果を示す図である。 尚図において、11……半導体基板、12……
フオトレジスト層、13……フオトレジストパタ
ーン、14……金属膜、14′……金属膜の残
り、31……半導体基板、32……フオトレジス
ト層、33……フオトレジストパターン、34…
…金属膜、35……金属膜の亀裂。
1a to 1d and 2 are cross-sectional views of each process of a semiconductor device according to the conventional electrode wiring forming method, and FIGS. 3a to 3e are sectional views of the electrode wiring forming method of a semiconductor device according to the present invention. 4, 5, and 6 are cross-sectional views showing one embodiment of the present invention in the order of steps, and are diagrams showing the effects of the present invention. In the figure, 11...semiconductor substrate, 12...
Photoresist layer, 13... Photoresist pattern, 14... Metal film, 14'... Remains of metal film, 31... Semiconductor substrate, 32... Photoresist layer, 33... Photoresist pattern, 34...
...Metal film, 35... Crack in metal film.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に2ミクロン以上の膜厚のフオト
レジスト層を形成する工程と、該フオトレジスト
層を選択的に露光・現象し、フオトレジストパタ
ーンを形成する工程と、該フオトレジストパター
ンを含む前記半導体基板に第一の熱処理を100℃
〜130℃で5分〜30分間行なう工程と、しかる後
スパツタリングにより電極配線となるべき金属膜
を被着する工程と、該金属膜を含む基板に第二の
熱処理を150℃〜250℃で20分〜60分間行なう工程
と、該基板をトリクレンで処理し、不要部分の該
金属膜及び該フオトレジストパターンを除去し、
電極配線のみを残す工程とを含むことを特徴とす
る半導体装置の製造方法。
a step of forming a photoresist layer with a thickness of 2 microns or more on a semiconductor substrate; a step of selectively exposing and developing the photoresist layer to form a photoresist pattern; and a step of forming a photoresist pattern on the semiconductor substrate. First heat treatment on the substrate at 100℃
A process of heating the metal film at ~130°C for 5 to 30 minutes, followed by a process of depositing a metal film that will become the electrode wiring by sputtering, and a second heat treatment on the substrate containing the metal film at a temperature of 150°C to 250°C for 20 minutes. a step of carrying out the process for 60 minutes to 60 minutes, and treating the substrate with Triclean to remove unnecessary parts of the metal film and the photoresist pattern,
1. A method of manufacturing a semiconductor device, comprising: a step of leaving only electrode wiring.
JP17352380A 1980-12-09 1980-12-09 Manufacture of semiconductor device Granted JPS5796551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17352380A JPS5796551A (en) 1980-12-09 1980-12-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17352380A JPS5796551A (en) 1980-12-09 1980-12-09 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5796551A JPS5796551A (en) 1982-06-15
JPS6258542B2 true JPS6258542B2 (en) 1987-12-07

Family

ID=15962097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17352380A Granted JPS5796551A (en) 1980-12-09 1980-12-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5796551A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4539222A (en) * 1983-11-30 1985-09-03 International Business Machines Corporation Process for forming metal patterns wherein metal is deposited on a thermally depolymerizable polymer and selectively removed

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394184A (en) * 1977-01-28 1978-08-17 Fujitsu Ltd Pattern forming method by lift-off

Also Published As

Publication number Publication date
JPS5796551A (en) 1982-06-15

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