JPS6260185A - Formation of bubble memory chip - Google Patents

Abstract

PURPOSE:To improve the yield of memory chips by deleting simultaneously both the insulated layer coated on a terminal part of a bonding pad, etc. set on a wafer and the insulated layer coated on a dicing line. CONSTITUTION:When a bubble memory chip is formed on a wafer 1, a terminal related to a pattern 21 is formed on an insulated layer 13 together with the pattern 21. Then the entire surface of the terminal 22 is covered with the 2nd insulated layer 23 like the pattern 21. While a terminal 26 related to a pattern 25 is formed on an insulated layer 23 together with the pattern 25. Then the entire surface of the terminal 26 is covered with the 3rd insulated layer 27 like the pattern 25. Here the dicing lines 3 set among memory chips for dicing are also covered with laminated layers 13, 23 and 27. Then the resist is coated over the entire surface of the layer 27 and undergoes the exposure and development excepting a window part. Then the insulated layers are removed by etching and terminals 22 and 26 are exposed. While the insulated layers 13, 23 and 27 coated over the lines 3 are also removed. In such a way, the yield is improved with the memory chips.

Description

[Detailed Description of the Invention] [Summary] When the insulating layer is peeled off during dicing of the wafer, and the peeling extends to the pattern forming area, the chips become defective.

Therefore, the insulating layer on the dicing line is removed in advance,
This eliminates the peeling of the insulating layer that occurs due to dicing.

[Industrial application field]

The present invention relates to a method for manufacturing a bubble memory chip (hereinafter referred to as a memory chip), and more particularly to a method for forming a memory chip that enables improved yield.

Figure 2 is a diagram for explaining the layer structure of a memory chip.
Figure 2 (al is a plan view of a wafer on which a plurality of memory chips are formed, and Figure 2 (b) is an enlarged cross-sectional side view of the memory chip. The same objects are represented by the same symbols throughout the plan. .

As shown in FIG. 2 (al), a plurality of (
IN memory chips 2 are formed at the same time, and dicing lines 3 for dividing the memory chips 2 into individual pieces are provided between the respective memory chips 2. After testing the characteristics of each chip in this state, dicing is performed to divide it into individual chips.

As shown in FIG. 2(b), the wafer 1 consists of a substrate 11 made of gadolinium gallium garneft and a single crystal layer 12 of magnetic garnet formed thereon, and the entire surface of the single crystal JiJ 12 is covered with a first silicon dioxide layer. (SiO2)
On top of the thin film (hereinafter referred to as an insulating layer) 13, various patterns for forming the memory chip 2 are formed on two mask levels.

At the first mask level, a pattern 21 made of a conductor mainly made of aluminum, such as a generator gate or a transfer gate, is formed on the insulation R13, and the entire surface of the pattern 21 is covered with the second insulation layer 23.

At the second mask level, minor loops, major lines, detectors, etc. are placed on the insulation WI23 using permalloy (Fe).
-Ni alloy) is formed, and its entire surface is covered with a third insulating layer 27.

In this way, various thin films are formed in layers on the wafer l by sputtering, but the adhesion between these thin films is not necessarily strong and peeling may occur with a slight impact. For example, when an impact is applied to the insulators [13, 23, and 27 during dicing, peeling occurs, and if the peeling extends to the patterned portion, the chip becomes defective.

Therefore, in order to improve the yield of memory chips, it is necessary to form memory chips on a wafer that have an independent layer structure for each chip, without applying force to the thin film that would cause peeling during dicing.

[Conventional technology]

FIG. 3 is a cross-sectional view showing a conventional method for forming a memory chip.

In the figure, the terminal 2 associated with the pattern 21 shown in FIG.
2 is formed on the insulating layer 13 together with the pattern 21, and like the pattern 21, the entire surface is covered with the second insulating layer 23. Further, a terminal 26 related to the pattern 25 shown in FIG. 2 is formed on the insulating layer 23 together with the pattern 25,
Similar to the pattern 25, the entire surface is covered with a third insulating layer 27. The dicing line 3 provided between memory chips in preparation for dicing also includes an insulating layer 13 deposited in layers.
．． 23, and 27.

In the wafer, which is entirely covered with the insulating Jii 27 in this manner, windows are opened in the insulating layer of the terminal portion according to the process shown in FIG. That is, a resist is applied to the entire surface of the insulating layer 27, exposed and developed except for the window portions, and then etched to remove the insulating layer and form the terminals 22 and 2.
6 is exposed. After testing the characteristics of each chip in this state, dicing is performed to divide it into individual chips.

[Problem that the invention seeks to solve]

However, a memory chip formed by a conventional method consists of a wafer 1, an insulating layer 13, 23 deposited thereon, and a
7 was diced at the same time, and there was a problem in that the impact during dicing was applied to each insulating layer, resulting in peeling that extended to the pattern forming area.

[Means for solving problems]

FIG. 1 is a sectional view showing a method for forming a memory chip according to the present invention.

The above problem occurs when forming the bubble memory chip 2 on the wafer 1 shown in FIG. This problem is solved by the memory chip forming method according to the present invention in which the insulating layers 13, 23 and 27 deposited on the dicing line 3 provided in the dicing line 3 are removed at the same time.

[Effect]

In Figure 1, by removing the insulating layer on the dicing line in advance together with the insulating layer on the terminal part, the force that causes peeling during dicing can be removed from the thin film. Memory chips having an independent layer structure for each chip can be formed on a wafer without being added, and the yield of memory chips can be improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to FIG.

In the figure, the terminal 2 associated with the pattern 21 shown in FIG.
2 is formed on the insulating layer 13 together with the pattern 21, and like the pattern 21, the entire surface is covered with the second insulating layer 23. Further, a terminal 26 related to the pattern 25 shown in FIG. 2 is formed on the insulating layer 23 together with the pattern 25,
Similar to the pattern 25, the entire surface is covered with a third insulating layer 27. The dicing line 3 provided between memory chips in preparation for dicing also includes an insulating layer 13 deposited in layers.
．． 23, and 27.

For the wafer, which is entirely covered with the insulating layer 27 in this way, windows are opened in the insulating layer at the terminal portion and in the insulating layer on the dicing line according to the process shown in FIG. That is, the insulating layer 27
A resist is applied to the entire surface of the substrate, exposed and developed except for the window portions, and then etched to remove the insulating layer and expose the terminals 22 and 26. Also, the insulating layers 13, 23 and 2 deposited on the dicing line 3
7 is also removed at the same time. After testing the characteristics of each chip in this state, dicing is performed to divide it into individual chips.

When the memory chips formed by this method are diced, the insulating layers 13, 23 and 27 deposited on the wafer 1 are removed in advance in the process, and are peeled off during dicing. The force that causes this is not applied to the FJ crotch. That is, memory chips having an independent layer structure for each chip can be formed on a wafer, and the yield of memory chips can be improved.

Moreover, since the insulating layer adhering to the dicing line 3 is removed in the process of the existing window, there is no need to add a new process for the window.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a method for forming a memory chip that enables improved yield.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing the memory chip forming method according to the present invention, Fig. 2 is a diagram for explaining the layer structure of the memory chip, - Fig. 2 (al is a plan view of the wafer, Fig. 2 (b) ) is an enlarged cross-sectional side view of a memory chip, Figure 3 is a cross-sectional view showing a conventional memory chip forming method, and Figure 4 is a work process diagram in the window. In the figure, ■ is a wafer, 2 is a memory chip, 3 is a dicing line, 11 is a substrate, 12 is a single crystal layer, 13, 23, and 27 are insulating layers, 2I, 25 are conductive patterns, and 22.26 are terminals. (12) Top view of Momme-Ha

Claims (1)

[Claims] When forming a bubble memory chip (2) on a wafer (1), an insulating layer (23 and 27) deposited on a terminal portion (22) such as a bonding pad, etc. The insulating layer (13, 23, and 27) is deposited on the dicing line (3) provided between the chip and the dicing line (3).
A bubble memory chip forming method characterized by simultaneously removing and.