JPS6260366A - Video signal binarization device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION - (Industrial Application Field) The present invention relates to a technique for extracting a video signal from a composite video signal in which the video signal is digitized.

(Prior art) Small computers such as game machines and personal computers use television receivers as display devices, so while they digitize video signals, they also mix water synchronization signals and vertical synchronization signals with video signals. The device is configured to output a composite video signal obtained by

To extract a video signal from such a composite video signal, a video signal extraction circuit consisting of an alternating signal extraction circuit to which the composite video signal is input and a transistor that detects the signal level from this circuit is used. Detection was performed by setting the output to a reference level and turning the transistor ON-OFF. However, since the output of the alternating signal extraction circuit depends on the magnitude of the input video signal, there is a problem in that errors occur in detecting video reliability.

(El-like) In view of such problems, one object of the present invention is to provide a video signal binarization circuit that can extract a video signal from a composite video signal regardless of the human power level.

(Means for Solving the Problem) That is, the present invention is characterized in that the peak voltage and pedicle voltage level of the +111 signal are set to 2. (The point is that it was made to be at a quasi-level.

(Example) The details of the present invention will be described below based on illustrated examples.

FIG. 1 shows an embodiment of the present invention, in which reference numeral 1 denotes a signal extraction circuit that extracts an input composite video signal using its pedestal voltage level as a boundary;
It outputs only the alternating components of the composite video signal input from the . 3 is a synchronization signal level detection circuit, and reference numeral 4 in the figure is an analog switch that opens and closes in synchronization with an output signal from a comparator 8, which will be described later, and sends a signal from the signal extraction circuit 1 to the voltage holder 5. While outputting, the voltage follower circuit 6
The signal is configured to be output to the reference level setter 7 via the reference level setter 7. Reference numeral 8 designates the above-mentioned comparator; the signal terminal receives the output signal from the signal extraction circuit 1, the reference terminal receives the output value from the reference level setter 7, and the signal from the signal extraction circuit 1 is inputted to the reference terminal. It is configured to output a synchronizing signal when the level falls below a reference level.

Reference numeral 9 denotes a delay circuit consisting of a multivibrator or the like, which delays the synchronizing signal from the synchronizing signal level detection circuit 3 by a time approximately corresponding to the pulse width of the horizontal synchronizing signal.

10 is a threshold voltage setting circuit, and the reference numeral 11 in the figure is an analog switch, into which the signal from the delay circuit 9 is input to the control terminal, and which outputs the signal output from the signal extraction circuit 1 to the subsequent circuit. It is something. 12 is a voltage holder that holds the voltage output from the analog switch 11; 13 is an operational amplifier; one input terminal receives the voltage of the voltage holder 12; the other terminal receives the synchronization signal level detection circuit 3. The peak level signal from the synchronizing signal is inputted, and the difference between the pedestal voltage level and the peak level of the synchronization signal is added to the pedestal voltage level and output. 14 is
In the comparator, the signal from the signal extraction circuit 1 is inputted to one input terminal, the signal from the threshold voltage setting circuit 10 is inputted to the other input terminal as a reference value, and the signal from the signal extraction circuit 1 is inputted as a reference value. '' is configured to output an H level signal when the second cycle occurs.

Next, the operation of the circuit configured as described above will be explained based on the waveform diagram shown in FIG.

When a composite video signal is input to the input terminal 2 (T in the figure), the signal extraction circuit 1 converts the input composite video signal into a signal whose pedestal level is about 0'iff, and outputs the signal. In such a state, when a synchronization signal that changes significantly to the negative polarity side is input, the signal extraction circuit 1 outputs a negative polarity pulse signal corresponding to the synchronization signal. The comparator 8 receives this pulse signal, and since it is smaller than the reference value, it outputs an H level signal and turns on the analog switch 4.

When the analog switch 4 is turned on, the synchronizing signal component output from the signal extraction circuit 1 is input to the voltage holder 5.

When the duration of the synchronization signal has elapsed, an L level signal is output from the comparator 8, the analog switch 4 is turned off, and the peak voltage of the synchronization signal is maintained (see Figure 2). This voltage is input to the level setter 7 via the voltage follower circuit 6 and is converted to a voltage level lower than the peak voltage of the synchronizing signal from the signal extraction circuit 1. Input to the reference terminal. As a result, the synchronization signal level detection circuit 3 holds the peak voltage of the horizontal synchronization signal in the voltage holder 5, and compares the composite video signal input from the subsequent horizontal scanning period with the signal from the level adjuster 7. Outputs a synchronization signal.

The synchronization signal detected in this way is input to the delay circuit 9, and the analog switch 11 is turned on immediately after the synchronization signal ends (II in the same figure). is extracted and voltage holder 1
2.

The operational amplifier 13 receives the synchronizing signal peak voltage from the synchronizing signal level detection circuit 3 and the bedlist signal level voltage from the threshold voltage setting circuit 10 and outputs the calculated voltage ΔV to the comparator 14 . The comparison circuit 14 sets a voltage having a level intermediate between the Bedistal voltage level of the composite video signal and the peak level of the video signal as a detection setting value, and sets the H level when the video signal from the signal extraction circuit 1 exceeds the reference level. , and outputs the L level when the voltage drops below the level.

Hereinafter, in this way, the synchronization signal level detection circuit 3 detects the peak level of the horizontal synchronization signal, and the threshold voltage setting circuit 10 detects the pedestal voltage level, and constantly calculates the peak level of the synchronization signal and the bedicle level. The voltage ΔV is output to the comparator 14 as a reference value. As a result, the reference value is set between the Bedistal voltage level and the peak level of the video signal, regardless of the level fluctuations of the input composite video signal, and the binarized video is generated regardless of the level fluctuations of the input composite video signal. signal can be extracted.

(Effects) As explained above, according to the present invention, the peak level and bedside voltage level of the synchronization signal are detected, and the differential voltage between these two signals is used as the reference level of the binary signal. The reference level can always be set between the pedestal voltage level and the video signal peak level, and the video signal can be detected with high accuracy regardless of level fluctuations in the composite video signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus showing an embodiment of the present invention;
FIG. 2 is a waveform diagram showing the operation of the above device. 1... Signal extraction circuit 3... Synchronous signal level detection circuit 4... Analog switch 10... Threshold voltage setting circuit 11... Analog switch 13... Operational amplifier ζ112 Aie Suj Seikosha

Claims (1)

[Claims] means for detecting the peak level of the composite video signal, means for detecting the pedestal level of the signal, arithmetic means for calculating the outputs of both the means, a composite video signal connected to one terminal,
A video signal binarization device comprising a comparison means to which the output from the calculation means is input to the other terminal.