JPS6260672B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flasher tester that accurately measures pulse signals, including group periods, emitted from flashing devices that control the quality of lights such as light buoys and marker lights. For example, the quality of lights such as various light buoys and beacon lights used for navigational aids and dangerous area indications has diversified to include single flashes, sudden flashes, group flashes, and Morse code lights in order to improve recognition. The light quality of such lights is given by digital signals, and in recent years, there has been a growing demand for highly accurate single period, group period, light time, rest time, etc. for the light quality of these lights. Therefore, it is necessary to accurately detect and measure their single period, group period, light time, and rest time, and adjust them to meet the standards. Conventionally, these time measurement methods have been carried out using mechanical or electronic stop watches, but not only are these methods insufficient in terms of accuracy, but there is no device that can measure arbitrary group periods. The present invention provides a device that makes it possible to measure each of bright time, rest time, single period, and group period using logic circuit elements, and furthermore, the complicated switching circuit for these measurement modes can be reduced to just a few minutes. This invention relates to a light time, rest time, single period, and group period measuring instrument constructed from circuit elements, and can of course also be used for general pulse signal measurement. Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram and timing chart shown in the drawings. Generally, to measure the pulse width and period of a digital signal, a gate control signal is created that corresponds to the pulse width or period time of the pulse signal to be measured, and then a highly accurate clock pulse _CP0 is blocked and passed. It is sufficient to count the number of ₀ pulses with a counter and display the count contents on a numerical display such as an LED. FIG. 1 is a block diagram showing the basic configuration of the present invention. As shown in the figure, a waveform shaping section 1 , a gate control section 2 that generates a gate control signal corresponding to the width or cycle time of an input pulse, and a clock pulse generation circuit (for example, The waveform shaping circuit 1 includes a crystal oscillation circuit) 3' and a gate circuit 3 '' to perform counting and display.The waveform shaping circuit 1 is configured, for example, when an input signal reaches a predetermined level by an input signal level determination circuit. It is composed of a CR wave circuit or unnecessary pulse removal circuit that responds appropriately to the input signal and eliminates the effects of unnecessary spikes included in the input signal and hazards during code synthesis, and converts it into a shaped rectangular wave. It serves to send data to the gate control section 2.The gate control section 2 , as shown in the circuit diagram of FIG. ) 7 and counter (below)
(abbreviated as CNT) 8. One of the two input terminals of the coincidence logic gate 4 is a program switch SW1 with a period measuring contact P, a rest time measuring contact S and a light time measuring contact M.
It is connected to the positive terminal 9 of the power supply via M and P of a, and the other input terminal is connected to the output terminal of the waveform shaping section 1 , so that the output signal a is supplied thereto. The output terminal of the coincidence logic gate 4 is connected to the clock pulse input terminal CP of the D-FF7, and the output signal b of the gate 4 is supplied to the terminal CP of the D-FF7. One input terminal of the two input terminals of the NOR gate 5 is equipped with a period measurement contact P', a rest time measurement contact S', and a light time measurement contact M'. It is connected to the positive terminal 9 of the power supply through the terminal. The other input terminal is connected to the output terminal of the coincidence logic gate 4 and receives the signal b.
are now being supplied. The output terminal of the NOR gate 5 is connected to the reset terminal _R1 of the D-FF7, and the output signal d of the gate 5 becomes the reset signal of the D-FF7. Also, one of the two input terminals of the AND gate 6
One input terminal is connected to the output terminal of the coincidence logic gate 4 so that its output signal b is supplied, and the other input terminal is connected to the output terminal of the coincidence logic gate 4.
It is connected to contacts S' and M' of SW1b. The output terminal of the AND gate 6 is connected to the set terminal _S1 of the D-FF 7 to supply a set signal e. The clock input terminal CL of CNT8 is connected to the output terminal of coincidence logic gate 4 and is supplied with signal b, and the reset terminal _R2 is connected to the output terminal of D-FF7 and its signal M is supplied. has been done. _The output terminals _Q1 , _{Q2 ,} . From another output terminal Q of the D-FF7, a signal K becomes a gate control signal and is sent to the counting section 3 . The coincidence logic gate 4, the NOR gate 5, and the AND gate 6 operate as "H" inputs when a power supply voltage is applied to their input terminals, and are determined to be "L" inputs when their inputs are open. The counting section counts and displays the clock pulses _CP0 passed by the gate control signal K. In the above configuration, when measuring the group period, the number of lighting signals can be recognized by a person, so the preset switch SW ₂ is operated to set the lighting number to that number. When measuring the group period of n lighting times (for example, 3 lighting times), set the preset switch _SW2 to _Qo = 3, and set the program switches SW1a and SW1b to the P and P' contacts. Set to . By doing this, one input terminal of each of the coincidence logic gate 4 and the NOR gate 5 is set to the "H" state, and one input terminal of the AND gate 6 is set to the "L" state. becomes. As a result, gate 4 becomes equivalent to a buffer gate, and its output signal b outputs the same as the other input signal a. The NOR gate 5 outputs "L" regardless of the other input signal, and the AND gate 6 also outputs "L" regardless of the other input signal, and the reset terminal _R1 and set terminal of D-FF7 are respectively connected.
This is equivalent to connecting S ₁ to the negative terminal of the power supply. Therefore, program switches SW1a, SW
1b to the period measurement contacts P and P', the second
The gate control signal generating section 2 shown in the figure is equivalent to the circuit shown in FIG.
The input signal a is supplied as is to the terminal CL of D.
- Since terminals S ₁ and R ₁ of FF7 are both held in the "L" state, it operates as a D-FF. In this case, in terms of logic, the D-FF7 takes in the signal at the data input terminal D at the rising edge of the signal at the clock pulse input terminal CP and sends it out as it is as the gate control signal K, and the output M is in an inverse relationship with the output K. In addition, in CNT8, all outputs Q ₁ , Q _{2 .} . . Q _o become “H” with the “H” signal of the reset terminal R ₂ ,
When the reset terminal _R2 signal is “L”, the count operation is performed at the falling edge of the clock input terminal CL signal,
When the first clock signal (A) is input, the output of _Q1 becomes "L", and when the third clock signal (C) is input, the output of _Q3 becomes "L".
becomes. FIG. 8C shows a timing chart at this time. First, since the CNT8 is not counting, the output signal N is "H". Gate control signal K
and M reads "H" of the signal N at the first rising edge of the signal a and sends it to the terminal Q as it is.
Therefore, the gate control signal K becomes "H" and the signal M becomes "L". At that timing, the reset of CNT8 is released. As a result, the output signal N of CNT8
is 3 from the pulse of signal a applied to terminal CL.
The state of "H" is maintained until the falling edge of the second pulse. Therefore, the output terminal Q of D-FF7
The gate control signal K changes from the "L" state to the "H" state at the rising edge of the first pulse "I" of the input signal a, and returns to the "L" state at the rising edge of the fourth pulse "I". The period during which this gate control signal K remains in the "H" state corresponds to the period T3 of a group of three pulses scheduled to be measured by indicating the number of lights on, and during this period the counting section ₃ receives clock pulses. CP ₀ will be counted and displayed. When the gate control signal K becomes "L" at the rising edge of the fourth pulse I', the output signal M at the output terminal becomes "H", CNT8 is reset, and the output signal N becomes "H". Thereafter, the above operation is repeated. When measuring the period of two pulses as a group, if Q _o of preset switch SW ₂ is set to 2, the two pulses are measured in the same order as above as shown in the timing chart shown in Figure 8B. period as one group
_T2 can be measured. When measuring a single period, _Qo may be set to 1, and the timing chart is shown in FIG. 8A. When measuring the light hours, set the program switch.
By setting SW1a and SW1b to M and M', the D-FF 7 operates as an RS flip-flop (hereinafter abbreviated as RS-FF) 7 without losing its function as a D-FF. Also, by operating this switch, one input terminal of the coincidence logic gate 4 goes "H", one input terminal of the NOR gate 5 goes "L", AND
"H" is always applied to one input terminal of the gate 6. Accordingly, the coincidence logic gate 4 becomes equivalent to a buffer gate due to its logic, and the output signal b outputs the same as the other input signal a. The NOR gate 5 is equivalent to the inverter gate 5 by logic, and the output signal d is "L" when the other input signal b is "H", and "H" when the input signal b is "L". ” is output. The AND gate 6 is logically equivalent to a buffer gate, and the output signal e is the other input signal b, so in this case, it outputs the input signal a as it is. As a result, in this case, the gate control signal generating section 2 of FIG. 2 is equivalent to the circuit shown in FIG. 4, and the D-FF 7 operates as an RS-FF 7 unrelated to the output N of the CNT 8. The circuit shown in FIG. 4 can be further replaced with the equivalent circuit shown in FIG. 5, and the timing chart thereof becomes as shown in FIG. That is, when the input signal a is "L", R-S-
The signal d applied to the reset terminal _R1 of FF7 is "H" and resets the RS-FF7, and the set terminal
Since the signal e applied to _S1 is the signal a itself, it is "L", and therefore the output gate control signal K of the output terminal Q of R-S-FF7 is "L" and the counting section 3 does not operate. When the input signal a becomes "H", the signal d is inverted and becomes "L", R-S-FF7
is released from reset and the signal a of "H" is applied to the set terminal _S1 , so the output signal K becomes "H", and this signal becomes the gate control signal K, and this gate control signal K is sent to the counter 3 . Sent, counting section 3
is counted and displayed based on clock pulse CP ₀ . When the input signal a returns to "L" after the elapse of one pulse time _t1 , the signal d is inverted and becomes "H", and the gate control signal K becomes "L", so that the counter 3
pauses counting. This process is repeated from now on, but the gate control signal K
The t ₁ hour in the "H" state indicates the light time of the light, and this allows the light time of the light to be measured accurately. When measuring rest time (dark time), by setting program switches SW1a and SW1b to S and S', D-FF7 does not lose its function as D-FF and operates as R-S-FF7. do. That is, by this switch operation, the coincidence logic gate 4
"L" to one input terminal of NOR gate 5, "L" to one input terminal of AND gate 6, "H" to one input terminal of AND gate 6.
is always held. Therefore, the coincidence logic gate 4 is logically equivalent to an inverter gate,
The output signal b outputs "L" if the other input signal a is "H", and outputs "H" if the input signal a is "L". The NOR gate 5 is equivalent to an inverter gate by logic, and its output signal d is "L" when the other input signal b is "H", and "L" when the input signal b is "L". Outputs “H”.
The AND gate 6 is equivalent to a buffer gate depending on the logic, and the output signal e outputs the other input signal b as it is. Therefore, in this case, the gate control signal generating section 2 of FIG. 2 becomes equivalent to the circuit shown in FIG. 6, and the D-FF 7 operates as the RS-FF 7. The circuit shown in FIG. 6 can be further replaced with the equivalent circuit shown in FIG. 7, and the timing chart thereof becomes as shown in FIG. That is, when the input signal a changes from the "H" state to the "L" state, the reset terminal _R1 of R-S-FF7
The signal d applied to becomes “L” and the set terminal
Since the signal e applied to S ₁ becomes "H", the gate control signal K at the output terminal Q becomes "H", and this signal is sent to the counting section 3 , and the counting section 3 operates based on the clock pulse CP ₀ . count and display. t When input signal a changes from "L" state to "H" state after ₂ hours, signal d becomes "H" and signal e changes to "H" state.
is "L", so the gate control signal K becomes "L", and the counting section 3 stops counting. This indicates that the input signal a is "L", that is, the dark state in which the lamp is off, that is, the pause time is counted and displayed by the counter 3 . As described above, according to the present invention, although there is a need for measurement, the group period, which has been difficult to measure with conventional counter devices, can be measured by a plurality of long and short blinking code lights such as Morse code lights, etc. In addition, it is possible to easily and accurately measure a group period in which a plurality of pulse signals with different pulse widths are grouped into one group using a minimum circuit configuration that utilizes the logic of circuit elements. In addition, it is possible to measure single period, light time, rest time, etc. with a single device, and the measurement mode switching circuit is made possible by a small circuit configuration that utilizes logic. . Based on the above, the group period of the light signal, the time to a single period or any signal of one group, or the light time,
Any pause time or the like can be easily measured by switching a switch.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic circuit configuration of the present invention, FIG. 2 is a gate control signal generation circuit diagram, and FIG. Equivalent circuit diagrams when set to measurement contacts P and P', Figures 4 and 5 are program switch SW1a,
Equivalent circuit diagrams when SW1b is set as contacts M and M' for measuring bright time. Figures 6 and 7 show program switches SW1a and SW1b as contacts S for measuring rest time,
FIGS. 8 to 10 are timing chart diagrams showing an equivalent circuit diagram for measuring the pause time when S' is set. 1 ...Waveform shaping section, 2 ...Gate control section, 3 ...
...Counting unit, 4...Concordance logic gate, 5...NOR
Gate, 6...AND gate, 7...D-FF(R
-S-FF), 8...CNT, 9...Positive terminal of power supply.

Claims (1)

[Scope of Claims] 1. A waveform shaping section that shapes a pulse signal under test applied to an input terminal, a counter with a preset switch whose output is used as a clock pulse input, and a flip-flop whose data input is the counter output. , the reset terminal and the set terminal of the flip-flop are in the L state, the output is connected to the reset terminal of the counter,
A gate control section that outputs a pulse signal with a time width equal to the period of the signal under test as a Q output by presetting the number of pulses in one cycle of the pulse signal under test; A flash tester consisting of a counting section that counts and displays numbers.