JPS6263473A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance reliability, by providing a plurality of regular-polygon shaped holes or circular holes for source and drain contact holes. CONSTITUTION:A contact hole is divided into a plurality of holes. For example, an interval between the holes is made to be 4mum or more. At this time, the interval may not be necessary constant. Along a contact region, where a plurality of said contact holes 41 are arranged, a wiring aluminum region 42 and the entire region of a source region 43 are contacted. By dividing the contact holes, the formation of a pattern can be ensured without dispersion in size. Almost the entire surface of the source region 43 can be contacted with the wiring aluminum 42. the length of the periphery is not increased. Therefore, poor bonding can be prevented. The resistance of the source region 43 can be made low to almost the same degree when one long contact hole is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device including an improved MOS transistor.

(Prior art) In a MO5LSI using a silicon substrate, in a long and narrow MOS transistor with source and drain regions ω and ■ as shown in FIG.
0μ), the contact hole should be made long and thin (for example, 4μ x 52μ) to prevent the resistance of the source region from increasing due to the high resistance of the diffusion layer.
) to make contact with the wiring over the entire source region. In this case, misalignment of the mask,
Considering the expansion of the contact hole during etching, the width of the contact hole is set to, for example, 4 .mu.m to provide a margin between the contact hole, the gate 1, and the field. Here, 4 is Ag wiring.

However, such an elongated contact hole
The width of the contact hole tends to be different from that of a square one, and the width of the contact hole becomes uneven because the amount of light that wraps around during exposure increases and the sag of the resist during development or baking differs between the long and short sides. There is a problem. In order to achieve high integration, the distance between the contact hole and other patterns must be minimized, but this allows the position of the contact hole on the mask to be determined in advance by 11!
! The need arises.

Furthermore, when photo-etching a fine pattern on silicon dioxide using a negative resist, if the pattern to be etched is long and narrow (for example, 4 μ x 5
2μ) After development, the resist 20 may remain in a sawtooth shape as shown in FIG. 3(b), and the desired pattern may not be removed. In extreme cases, the resist 20 remains on the entire surface of the contact hole.

Of course, if the resist remains on the entire surface of the contact hole, the silicon dioxide will not be etched and electrical contact will not be established between the source region and the wiring.

Generally, for example, when heat treatment is performed to obtain good electrical contact after A1 wiring is provided, Al■ and silicon■ react locally in the vicinity of silicon dioxide 0 and diffuse M(
8) Alloy layer 0 penetrates through, causing p-'n junction failure.

Therefore, if the resist remains in a sawtooth shape and a fine mottled pattern is formed as shown in Figure 3(b),
If etching is normally performed on the shape of a), the relative length of the silicon oxide IIII will be extremely increased, increasing the probability of a pn junction failure due to penetration of the diffusion layer of the AQ-Si alloy layer.

As shown in Figure 7, this means that Sun, , (30) is 5i (
31) This is likely to occur when the wafer (32) provided above has a step and the adhesion between the mask (33) and the wafer (32) is not good.The cause of this is due to the subtle light during exposure. This is due to interference, and when cutting out a rectangular pattern (for example, 4μ x 8μ) as shown in Fig. 4 (Ca).

As shown in FIG. 4(b), the state of the resist zO after development shows that the central portion remains protruding inside the pattern, and this tends to be more emphasized in the central portion of the longer side.

As shown in Fig. 5(a), a square pattern (for example, 4μ×
4μ), the same effect occurs on all sides as shown in Figure 5(b), but this is almost the same effect as the effect on the short sides of the rectangle in Figure 4(b). , which is much smaller than the effect produced on the long side.

From this point of view, when photo-etching a fine pattern, it has been found that rectangles that are not elongated are preferable to elongated rectangles, regular polygons with a side number of 5 or more are preferable to rectangles, and circles are preferable to regular polygons.

(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and its purpose is to provide a semiconductor device including a highly reliable MOS transistor with an improved contact hole structure. There is a particular thing.

[Structure of the invention]

(Means for Solving the Problems) According to the present invention, source and drain contact holes are formed into a plurality of regular polygonal or circular shapes.

(Function) According to the present invention, reliability is increased because there are a plurality of contact holes.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

For example, in the case of the above-mentioned example shown in FIG. 2, if it is necessary to provide a long and narrow contact hole (for example, 4μ x 52μ), in this embodiment, instead of drilling a long and thin contact hole, as shown in FIG. is divided into a plurality of parts, and the distance between the two parts is, for example, 4 microns or more. In this case, the wiring aluminum (42) and the entire source region (43) are brought into contact through a contact region in which a plurality of contact holes (41), which do not necessarily need to be spaced at constant intervals, are arranged. Furthermore, in Figure 1,
(44) is a drain region, (45) is a gate, and the above-mentioned contact hole (41) is expanded by expanding some of these holes to connect adjacent contour foot holes, and making the contact hole (41) larger than the contact hole before expansion. It is also geometrically possible to group the contact holes into one or more contact holes that do not have a small width.

By dividing the contact hole in this way, it is possible to form a pattern reliably without any variation in one dimension.
In addition, the source region (43) is covered with wiring aluminum (
42), the peripheral length does not increase, and therefore junction defects can be prevented, and the source region (42)
The resistance in step 3) can also be made as low as in the case where one elongated contact hole is provided.

Here, in this embodiment, the contact hole shape is circular or polygonal with a side number of 5 or more. Therefore, since the contact hole pattern is symmetrical in all directions, there is no distortion caused by the asymmetry of the pattern, and extremely small holes can be made.

In this embodiment described above, an example was explained in which the source region and the wiring are in contact, but instead of the source region, a diffusion layer such as a drain region, a polycrystalline silicon or metal layer, or a conductive layer such as tungsten, molybdenum, aluminum, etc. If the area is within the scope of the present invention. Furthermore, although aluminum was used as the wiring in the above embodiment, the present invention can also be applied to examples in which metals other than aluminum, polycrystalline silicon, semiconductors, and all other materials that can be used as wiring materials are used as the wiring. Of course.

〔Effect of the invention〕

According to the present invention, a semiconductor device including a highly reliable MoS transistor can be obtained.

[Brief explanation of the drawing]

Figure 1 shows M when an improved contact hole is provided.
FIG. 2 is a plan view of an OS transistor, FIG. 2 is a plan view of a conventional MOS transistor, and FIGS. 3 to 5 each show a desired pattern to be photo-etched. FIG. 6 is an explanatory diagram showing a state in which resist remains in the pattern after development, FIG. 6 is a diagram showing poor bonding, and FIG. 7 is a diagram showing adhesion with a mask when there is a step on the wafer. 41... Contact hole, 42... AQ wiring. 43... Source region, 44... Drain region. 45...Gate. Agent Patent Attorney Nori Ken Yudo Takehana Kikuo Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] source and drain regions formed spaced apart from each other on a silicon substrate, a gate electrode provided between these source and drain regions, and an insulating film having a contact hole formed on the source and drain regions; A MOS comprising wiring formed in the contact hole from above the insulating film and in contact with the source and drain regions.
In a semiconductor device including a transistor, the contact holes on the source or drain region are formed of a plurality of circular or regular polygonal shapes with sides of 5 or more arranged at intervals in the direction in which the gate electrode extends. A semiconductor device comprising contact holes.