JPS6264037U - - Google Patents

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Publication number
JPS6264037U
JPS6264037U JP15563985U JP15563985U JPS6264037U JP S6264037 U JPS6264037 U JP S6264037U JP 15563985 U JP15563985 U JP 15563985U JP 15563985 U JP15563985 U JP 15563985U JP S6264037 U JPS6264037 U JP S6264037U
Authority
JP
Japan
Prior art keywords
flop
flip
circuit
clock signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15563985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15563985U priority Critical patent/JPS6264037U/ja
Publication of JPS6264037U publication Critical patent/JPS6264037U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

図はこの考案の一実施例によるタイマ回路の構
成図である。 10……入力回路、14……リードスイツチ(
入力信号源)、16……フリツプフロツプ、18
……出力回路、20……フオトカプラ、26……
カウンタ、28……波形整形回路(クロツク発生
回路)、30……パワーオンリセツト回路。
The figure is a configuration diagram of a timer circuit according to an embodiment of this invention. 10...Input circuit, 14...Reed switch (
input signal source), 16...flip-flop, 18
...Output circuit, 20...Photocoupler, 26...
Counter, 28... waveform shaping circuit (clock generation circuit), 30... power-on reset circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号の所定の変化を受けてセツトされるフ
リツプフロツプと、所定周期のクロツク信号を発
生する回路と、上記フリツプフロツプがセツトさ
れた時点から上記クロツク信号の計数を開始し、
計数値が設定値になつた時点で上記フリツプフロ
ツプをリセツトするカウンタと、上記フリツプフ
ロツプの出力を外部に導出する出力回路とを備え
たタイマ回路。
a flip-flop that is set in response to a predetermined change in an input signal; a circuit that generates a clock signal of a predetermined period; and a circuit that starts counting the clock signal from the time when the flip-flop is set;
A timer circuit comprising a counter that resets the flip-flop when the count value reaches a set value, and an output circuit that outputs the output of the flip-flop to the outside.
JP15563985U 1985-10-14 1985-10-14 Pending JPS6264037U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15563985U JPS6264037U (en) 1985-10-14 1985-10-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15563985U JPS6264037U (en) 1985-10-14 1985-10-14

Publications (1)

Publication Number Publication Date
JPS6264037U true JPS6264037U (en) 1987-04-21

Family

ID=31076515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15563985U Pending JPS6264037U (en) 1985-10-14 1985-10-14

Country Status (1)

Country Link
JP (1) JPS6264037U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516259A (en) * 1978-07-21 1980-02-04 Jeco Co Ltd Timer device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516259A (en) * 1978-07-21 1980-02-04 Jeco Co Ltd Timer device

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