JPS626487A - Memory ic constituted of plural data bits - Google Patents

Abstract

PURPOSE:To obtain easily a memory device having a write inhibiting function for inhibiting the writing of required plural bit units by including flip flops (FFs) corresponding to the number of data bits and a control circuit for controlling a writing clock in each bit. CONSTITUTION:The D-type FFs 1020-1023 inputting data d0-d3 to a data input terminal D and inputting the 1st clock signal phi1 to the clock input termi nal store the contents of the data d0-d3 respectively at the trailing edge of the 1st clock signal phi1. A writing clock signal phi3 is inputted to one input terminals of OR gates 1030-1033 to be used for writing clock control, outputs from the output terminals the inverse of Q of the FFs 1020-1023 are inputted to the other input terminals of the OR gates 1030-1033 respectively and respec tive output terminals are connected to the write enable input terminals the inverse of WE of memory arrays 1010-1013. Namely, each OR gate 103 inhibits the input of the writing clock signal phi3 in each memory array 101 in accordance with the contents of each FF 102 and inhibits the writing of data (d).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory IC having a plurality of data bits.

[Conventional technology]

Semiconductor memory ICs, especially dynamic MOS memory ICs, are generally used as memory ICs used in information processing devices, but in recent years, due to improvements in their degree of integration and diversification of applications, the conventional 1 data bit Dynamic MOS memory ICs with multiple data bit configurations are increasingly being used.

FIG. 4 is a block diagram showing an example of a conventional memory IC having a plurality of data bits configuration.

16 shows a memory IC having a word x 4 bit configuration. In the figure, #LOO' is a conventional memory IC, and 4
Memory array 101°, 1 IK word x 1 pit
01. ．． It is composed of 101□ and 1013. Each memory array 101 has seven address signals a0 to a,
seven address input terminals A0 to A, which input the first clock signal φ, a row address strobe input terminal RAS which inputs the first clock signal φ, a column address strobe input terminal CAS which inputs the second clock (lφ2), and a write It has a write enable input terminal WE which inputs a clock signal φ, and is commonly connected inside the IC 100'.

Each memory array 1010.101. ．． 101. and 101 have bidirectional data bit terminals D0, DI, D, and 101 for separately inputting and outputting data die led* and d4, respectively.

In addition to this, terminals for inputting signals for determining input and output of data bits are usually provided.

It is omitted in this figure.

Next, the write operation of the memory IC shown in FIG. 4 will be explained with reference also to the time chart shown in FIG.

This type of memory IC receives an address signal twice in a time-division manner. First, at the fall of the first clock signal φ1,
Address signals a0-a, row address signals r0-r
First, at the falling edge of the second clock signal φ2, the column address signals 00 to C6 are taken in as the address signal ILO"""a6.9 Addressing words in 16 with a total of 14 address signals. Further, the contents of data d.-d3 are written at the falling edge of the write clock signal φ.

[Problem that the invention seeks to solve]

The conventional memory IC with multiple data focus configuration described above has 4
Although it has a bit configuration, information processing devices that use this memory IC often use ? Since the IJ check method is adopted, a memory device having a configuration that can control writing in units of 9 bits may be required. Therefore, when using the above-mentioned memory IC in such a device, 1
It was also necessary to use a bit-structured memory IC.

For example, in order to be able to control writing in units of 9 bits in a memory device having a total of 36 pits.

Two 4-bit memory ICs and one 1-bit memory IC are combined to form a 9-bit memory IC.

It was necessary to use four sets of these. In this case 1. Normally, it is difficult to obtain a 1-bit configuration memory IC and a 4-bit configuration memory IC with the same number of words, so some bits of the memory IC may not be used, or the control circuit may be affected due to the difference in the number of address signal input terminals. There are drawbacks such as the complexity of the memory IC, or the complexity of the chip selection circuit when a plurality of memory ICs are used in the word direction.

[Means for solving problems]

The memory IC of the present invention incorporates seven lip-flops, the same number as the number of data bits, and a control circuit for controlling the write clock for each bit. The data input terminals of each of the seven 70 terminals are connected to data signals, and the output terminals are input to a control circuit that controls the write clock of each bit.

Further, the clock input terminal of each flip-flop is internally connected to a conventionally provided clock signal.

〔Example〕

Hereinafter, nine embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a memory I having a plurality of data bits according to the present invention.
This is a block diagram showing the configuration of an embodiment of C. This embodiment also shows a memory IJIC having a 16 word x 4 bit configuration. In FIG. 1, #10° is a memory IC having a structure of 16 words x 4 bits according to the present invention. 101°=1
01t y101□ and 1013 are memory arrays each having 16 words×1 bit. 102°, 10
2. ．． 102□ and 102. teeth.

Data d, d, respectively at the data input terminal.

d, and d3, and a D-type frizzo flop that inputs the first clock signal φ□ to the clock input terminal;
At the falling edge of the first clock signal φ, the data d
6 * dl * Store the contents of d2 and d3.

103. ．． 1031.103□ and 1033 are OR-DARTs used for write clock control, one input terminal of which receives the write clock signal φ3, and the other input terminal of each of which receives the D-type clip flow 2p 102. ．． 1
02□.

The outputs from the output terminals 102□ and 1023 are input, and the output terminals of the OR date are connected to the memory array 101, respectively.
゜, 1011.101□ and 1013 are connected to write enable input terminals WE. That is, each OR gate 103 largely prohibits input of the write clock signal φ3 to each memory array 101, and prohibits writing of data d, depending on the contents of each flip-flop 102.

FIG. 2 is a block diagram showing the configuration of a 20-pin memory device using the memory IC shown in FIG. 1, which requires write control for every 5 pins. As shown in the figure, there are four conventional memory ICs 100' and one memory IC 100 of the present invention.

In FIG. 2, 201 is a 7-bit signal switching circuit which changes the row address signal r in response to the clock signal φ4. −
Select r6 or column address signals C0 to C0. 202
is a 4-bit signal switching circuit, and the clock signal φ4
The write protect signal is set by the write protect signal. Select e1*b2 and s, or data d41d9, d□4 and dss.

203°.

203□, 2032 and 2033 are write inhibit signals b
O+b1 This is an OR gate that performs write control in 5-bit units according to mb2 and b3. 204° and 205 are tri-state circuits.

It is controlled by a clock signal φ.

The reverse signals φ□, φ2, and φ are signals corresponding to the row add strobe input terminal RAS, column address strobe input terminal CAS, and write enable input terminal WE of the memory ICs 100' and 100, respectively. Further, data d0 to d4, data d, to d, M data d1° to d1'4, and data d15 to ate are each write inhibit signals borb□.

This is a data group corresponding to b2 and s.

In this device, the data input to the conventional memo IJ IC100' are 0 to d8. Data d, ~d6. Write control of data d1° to d□ and data ats to dig is performed by write inhibit signals b (1*tllyb2 and b3, OR gates 203° and 2031, respectively).

This is done by 2032 and 2033 and the clock signal φ3. On the other hand, writing control of the data d4e @jd14 and dte input to the memo+7 IC100 of the present invention is a memo that is a feature of the present invention! This is performed by the bit-by-bit write control function of the JIC100.

This will be explained below with reference to FIG.

Referring to FIG. 3, at the time when the clock signal φ□ inputted to the 1st row address strobe input terminal 1 falls, the signal switching circuit 201 selects the address input terminals A0 to A0.
At the same time, the signal switching circuit 202 inputs write inhibit signals b0 to b3 to the bidirectional data bit terminals D0 to D.

This is stored in flip-flops 102° to 1023 within memory IC 100.

Next, when the clock signal φ4 is inverted, the signal switching circuit 2
01 is the column address signal C0 to C7, and the signal switching circuit 20
2 selects data d4 g d@ * a14jd□. Therefore, at the time when the clock signal φ input to the write enable input terminal W1 falls, the flip-flops 102° to 102. A write protect signal is stored in advance. ~b3 data ct41 d9
1 d14 and d□ are controlled within the memory IC 100.

In the above embodiment, a dynamic memory IC with a word x 4 bit configuration was used as an example, but memory ICs with other configurations or static memory ICs may also be used.
It goes without saying that the present invention can also be applied to C.

Furthermore, it is clear that the present invention can be used in applications other than memory devices that require write control in units of 5 bits as in the application example described above.

〔Effect of the invention〕

As is clear from the above description, according to the present invention.

By incorporating means for enabling write control for each bit in the memory IC, it is possible to easily configure a memory device having a desired write inhibit function in units of a plurality of bits.

[Brief explanation of drawings]

FIG. 1 shows a memory I having a plurality of data bits according to the present invention.
FIG. 2 is a block diagram showing the configuration of an embodiment of C. FIG. 2 is a block diagram showing an application example of the memory device using the memo+JIC shown in FIG. 1, and FIG.
A time chart for explaining the operation of the figure. FIG. 4 is a block diagram showing an example of the structure of a conventional memory IC having a plurality of data bits. FIG. 5 is a time chart for explaining the operation of FIG. 4. 100...Memo of multiple data bit configuration! 71C. 101°~1013...Memory array, 102°~1
023...Furiragurotsuno, 103°~103°・
... or f-). , -'100" 90 Figure 1 Figure 2 'O~'6 co% c6 Figure 3

Claims (1)

[Claims] 1. A memory IC having a plurality of data bit configurations operated by one write clock signal and at least one other clock signal, the memory IC having a plurality of data bit configurations operated by one write clock signal and at least one other clock signal, wherein the memory IC operates by one write clock signal and at least one other clock signal. It is characterized by incorporating the same number of flip-flops as the number of data bits that store information, and means for controlling the writing of information for each data bit by the write clock signal in accordance with the output of each flip-flop. A memory IC with a multiple data bit configuration.