JPS6266341A - Runaway detecting circuit for cpu - Google Patents

Abstract

PURPOSE:To detect the runaway of a CPU and to prevent a device from having a fatal problem by providing a CPU runaway detecting circuit between the CPU and a device to be controlled. CONSTITUTION:An oscillator 2 sends out a period T1a interruption signal to the CPU 1, which responds to it to send out signals S1 and S2 for setting and resetting a flip-flop 4 through a decoder 3. A monostable multivibrator 5 maintains a high level for a constant period (T1<T<2T1) longer than the interruption signal by the setting of the flip-flop 4 and a tri-state circuit 7 sends the signal from the CPU to a motor 9 through a driving circuit 8 during said period. When the CPU 1 runs away, neither of the response signals S1 and S2 from the CPU by the interruption signal is obtained, the monostable multivibrator 5 is at a low level continuously, and the tri-state circuit 7 does not transmit the signal from the CPU to the driving device 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a device that uses a CPU to control an electric circuit.

(Background of the Invention) A device that uses a CPU to control loads such as motors etc. uses a program to control driver circuits, etc. to 0N10F.
Because of this, if the CPU were to run out of control due to noise or a short circuit during signal observation, the motor etc. would stop spinning and the device would be damaged.

(Object of the Invention) An object of the present invention is to solve these drawbacks and provide a runaway detection circuit that prevents fatal problems from occurring as a device even if the CPU goes out of control.

(Summary of the Invention) The present invention provides an interrupt signal output circuit 2 that controls a controlled device 9 and outputs periodic interrupt signals to the CPU 1, and that the CPU an alarm that generates at least one control signal (see the flowchart in FIG. 2) and maintains a predetermined level by the control signal for a predetermined period longer than the period of the output signal of the interrupt signal generation circuit; An alarm signal generation circuit (3, 4, 5) that outputs a signal S4 is provided, and the CPU
A CP characterized by detecting whether or not the is running out of control.
This is the U runaway detection circuit.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention, in which the CP
An example is shown in which the rotation of the motor 9 is controlled by U1.

For example, the interrupt input terminal of CPU1 (including this if interrupt input is performed by a dedicated LSI) has a value of 100.
An oscillator 2 is connected which outputs clock pulses of Hz. An address decoder 3 is connected to the address bus of the CPU 1, one of the output terminals of the address decoder 3 is connected to the set terminal S of the flip-flop 40, the other one is connected to the reset terminal R of the flip-flop 4, and The other one is connected to the clock terminal CK of the D flip-flop. The output terminal of the flip-flop 4 is connected to the input terminal of the monomulti 5 of the Ridrigger. The monomulti 5 outputs a pulse having a predetermined pulse width T in response to a pulse generated at its input terminal. This pulse width T is
The relationship with the period T1 of the clock pulse output from the oscillator 2 is 'r,<T<2TI. mono multi 5
The output terminal of is connected to the control terminal of the three-state circuit 7.

A data bus of the CPU 1 is connected to a D terminal of a D flip-flop 6, and an output terminal of the D flip-flop 6 is connected to an input terminal of a three-state circuit 70. In the three-state circuit 7, the output terminal is pulled down, the control terminal has a high-level frontage impedance, and the high-level signal (motor rotation command) of the input terminal is transmitted to the output terminal, and the control terminal is low-level. When the level is reached, the impedance becomes high and prevents the high level signal at the input terminal from being transmitted to the output terminal. An output terminal of the three-state circuit 7 is connected to an input terminal of a drive circuit 8, and an output terminal of the drive circuit 8 is connected to a motor 9.

The operation of this circuit will be explained below with reference to FIG. 2, which is a flow chart of the CPU 1, and FIG. 3, which is a time chart of the circuit.

(1) Oscillator 2 generates a 100 Hz pulse (
When the signal shown in FIG. 3(a) is input to the interrupt input terminal of the CPU 1, the CPU 1 is interrupted every 10 m5 (step 20 in FIG. 2). Note that the interrupt jump destination in step 20 is the jump destination when an interrupt is input to the CPU 1 by a pulse from the oscillator 2.

(II) When an interrupt occurs, the CPU 1 is controlled by the program and outputs a control signal to the address decoder 3 (for example, issues an OUT command to a predetermined address).

That is, first, step 2 is performed to output a control signal so that the address decoder 3 outputs the signal S1 (FIG. 3(b)) for setting the flip-flop 4.
1], followed by a signal S2 for resetting the flip-flop 4 from the address decoder 3 (Fig. 3(b)).
] is output (step 22).

011) Therefore, the pulse S3 is output from the flip-flop 4 in synchronization with the clock pulse of the oscillator 2 (the third
Figure (C)).

Ridriger mono multi 5 inputting 4ψ pulse S
Then, with the rise of pulse S3, pulse S4 having the above-mentioned pulse width is output as an alarm signal (Fig. 3(d)).
).

(v) The output of the pulse S4 brings the three-state circuit 7 into a low impedance state, that is, into a state where the output signal of the D flip-flop 6 is transmitted. And Mono Multi 5
As described above, the pulse width T of the pulse S4 output from the oscillator 2 is equal to the period T of the clock pulse of the oscillator 2.
Since the relationship is T<2T1, the three-state circuit 7 is always in a low impedance state when the CPU 1 is operating normally and is in a state of accepting interrupts from the oscillator 2.

That is, in FIG. 3, when the interrupt signal is generated at time t, and the signal S1 is generated at time t2, the flip-flop 4 is set, the monomulti 5 becomes high level, and the signal S1 is generated at time t2.
When the signal S2 occurs at 3, the flip-flop 4 is reset. The monomulti 5 should become low level at time t after 1.5T1 hours, but since the flip-flop 4 is set as above at time t4 before that, a new pulse 54-2 is generated by the redrigger function. is occurring, which is why it maintains a high level.

■ If CPU1 goes out of control, the above (11), (i
Since the ifl operation is no longer performed, the pulse S4 from the monomulti 5 disappears, and the three-state circuit 7 becomes high impedance. That is, since the flip-flop 4 is set at time t6 in FIG. 3, reset at time t, and then not set again, the pulse S4 is 1.5T from time t6 when the flip-flop 4 is last set.
After time, at time t8, it becomes low level.

Since the runaway detection circuit has such a configuration, when the OUT command from cpul to the D flip-flop 6 is executed to drive the motor 9, the CPU 1 detects that the decoder 3 is synchronized with the clock terminal CK of the D flip-flop 6. At the same time, a control signal for inputting the signal S is outputted, and at the same time, a rotation command signal S6 for the motor 9 is sent to the data bus.
As a result, the rotation command signal S6 becomes the synchronization signal S,
is stored in the D flip-flop 6 in synchronization with the . This rotation command signal S6 is transmitted to the motor drive circuit 8 through the three-state circuit 7, and the motor 9 rotates. Even if the CPU 1 goes out of control and the rotation command signal S6 is left out of the D flip-flop 6, the 3-state circuit 7 is activated immediately.)
Since the impedance becomes 1, the motor 9 stops.

In addition, in the above embodiment, the runaway detection circuit of the present invention is
1 was used in the circuit that drives the motor 9, but if the pulse from the monomulti 5 were used to light up a display element, for example, the C
You can know if PU1 is running out of control.

Furthermore, the signal S1 output from the address decoder 3,
S2 may be three or more signals. In this case as well, the combination of these signals generates an alarm signal of $4.
All you have to do is make it happen.

Furthermore, considering the aspect of outputting in response to pulses from the oscillator 2, the same state as the state when the CPU 1 is reset can be created when the CPU 1 runs out of control. for example,
In the above embodiment, the three-state circuit 7 and the driver 8
If a D-A converter is connected between the DA converter and the D-A converter, by pulling up or pulling down the human power of the D-A converter to an appropriate value, if CPU1 goes out of control, the load will be in the same state as when it was reset. I can do that.

(Effects of the Invention) As described above, according to the present invention, if for some reason the system is controlled by a program, etc.
If the PU runs out of control, a warning can be issued promptly, and the load such as a motor can be stopped electrically (not based on a program) before the operator notices the runaway, thereby preventing damage to the equipment. It is possible to promptly prevent accidents from occurring or resulting in human disasters.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a flowchart of a CPU program necessary for detecting a runaway of the PU, and is a time chart for explaining the operation of the circuit. (Explanation of symbols of main parts) 1 ... CPU 2 ... Oscillator 3 ... Address decoder 4 ... RS flip-flop 5 ... Ridrigger MonoMulti Applicant 2 Nippon Kogaku Kogyo Co., Ltd. Light Manufacturing Co., Ltd. Figure J

Claims (1)

[Claims] An interrupt signal output circuit for outputting periodic interrupt signals to a CPU that controls a controlled device is provided, and the CPU
U generates at least one control signal in response to the interrupt signal, and the control signal maintains a predetermined level for a predetermined period longer than the cycle of the output signal of the interrupt signal generation circuit. A CPU runaway characterized by providing an alarm signal generation circuit that outputs an alarm signal to be maintained, and detecting whether or not the CPU is running out of control depending on whether the alarm signal is at the predetermined level. detection circuit.