JPS627219A - Signal output circuit - Google Patents

Signal output circuit

Info

Publication number
JPS627219A
JPS627219A JP60147251A JP14725185A JPS627219A JP S627219 A JPS627219 A JP S627219A JP 60147251 A JP60147251 A JP 60147251A JP 14725185 A JP14725185 A JP 14725185A JP S627219 A JPS627219 A JP S627219A
Authority
JP
Japan
Prior art keywords
circuit
zener diode
input
gate
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60147251A
Other languages
Japanese (ja)
Inventor
Chifuyu Saegusa
三枝 千冬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60147251A priority Critical patent/JPS627219A/en
Publication of JPS627219A publication Critical patent/JPS627219A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a signal output circuit preventing surely malfunction with simple circuit constitution by connecting a connection circuit comprising a Zener diode and a resistor connected between a power supply and common to one input of a gate circuit. CONSTITUTION:The Zener diode 5 connected to a logic power supply +5V and a resistor 6 whose one terminal is connected to common are connected to one input (2) of the gate 2 comprising an open collector TTL IC. When the voltage of the logic power supply drops and is lower than the voltage of the Zener diode 5, since th Zener diode 5 carries no current, the level of the terminal (2) of the gate 2 is kept to a low level and its output goes to a high level. Then even when the input signal goes to any level, the output is kept to the high state, that is, the state of absence of signal to prevent malfunction.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフロッピディスク駆動(F D I) )装置
、D I S K装置等のTTLオーブンコレクタのI
″11ウアクテイブL OW  A CT I ■E 
>インターフェイスを持つ装置と制御回路とを別々の電
源により連動させて動作させる場合の信号出力回路に関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to TTL oven collector I of floppy disk drive (FDI) devices, DISK devices, etc.
″11 UACTIVE L OW A CT I ■E
>Related to a signal output circuit when a device having an interface and a control circuit are operated in conjunction with each other using separate power supplies.

し従来の技術〕 従来、このような制御回路とドライブ装置とをもつ回路
は、一般的に同一電源によって動作させることで本体制
御部もドライブ装置側も同時に電源をオン・オフさせる
ことによって誤動作を防止したり、リセットIC又はリ
セット制御回路によってロジック電圧が+5Vからある
程度低下すると(一般的には4.3〜4.0■が多い)
、インターフェイス回路部をカットオフし、論理信号イ
ンターフェイスと信号なしくノーアクティブ)とするこ
とによってその誤動作を防止していた。
Conventional technology] Conventionally, circuits with such a control circuit and a drive device are generally operated by the same power source, so that the main body control section and the drive device side are turned on and off at the same time, thereby preventing malfunctions. If the logic voltage drops from +5V to some extent by the reset IC or reset control circuit (generally 4.3 to 4.0■)
, the interface circuit section was cut off to prevent malfunctions by making it non-active (no signal with the logic signal interface).

第2図は従来の回路の一例であり、T T L負論理イ
ンターフェイスを5つ制御回路10にはリセット回路1
を接続したゲート回路(7438)2が出力回路となっ
ており、この出力はインターフェイス回路1]−3介し
てドライブ装置12の5V電源と接続された抵抗・1と
共に入力LSIBに接続されている。
FIG. 2 shows an example of a conventional circuit, in which there are five TTL negative logic interfaces, a control circuit 10, a reset circuit 1, and a control circuit 10.
The gate circuit (7438) 2 connected thereto serves as an output circuit, and this output is connected to the input LSIB together with a resistor 1 connected to the 5V power supply of the drive device 12 via the interface circuit 1]-3.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このように従来の回路は、本体制御回路側の電源オン・
オフ時の動作不安定領域での誤動作により記憶媒体の書
込電源による破壊を防止するため、本体1則ドライブ回
路10に専用リセット回路1を用いていたため、その回
路構成が複雑となっていた。
In this way, in the conventional circuit, the power is turned on and
In order to prevent the storage medium from being destroyed by the write power supply due to malfunction in the unstable operation region when turned off, a dedicated reset circuit 1 is used in the main body monolithic drive circuit 10, resulting in a complicated circuit configuration.

本発明の目的は、このような問題を解決し、簡単な回路
で確実に誤動作を防止した信号出力回路を提供すること
にある。
SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a signal output circuit that is simple and can reliably prevent malfunctions.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の信号出力回路の構成は、オープンコレクタ型ド
ライバーのゲート回路の一つの入力に、電源と接地との
間に接続したツェナーダイオードと抵抗との接続回路を
接続して構成され、前記ゲート回路の一方の入力をロウ
レベルに固定し誤動作を防止したことを特徴とする。
The configuration of the signal output circuit of the present invention is configured by connecting a connection circuit of a Zener diode and a resistor connected between a power supply and ground to one input of a gate circuit of an open collector type driver, and the gate circuit One of the inputs is fixed at a low level to prevent malfunction.

〔実施例〕〔Example〕

次に本発明を図面により詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第1図は本発明の一実施例の回路図である。図において
、オーブンコレクタTTLのICからなるゲート2の一
方の入力(2ンには、ロジック電源(+5V)と接続さ
れたツェナダイオード5と一端が接地された抵抗6とが
接続されている。このロジック電源の電圧が低下し、ツ
ェナーダイオニド5の電圧を下廻るとこのツェナーダイ
オード5は電流分流さないため、入力ゲート2の端子(
2)はロウに保持され、その出力はハイ状態になる。
FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, a Zener diode 5 connected to a logic power supply (+5V) and a resistor 6 whose one end is grounded are connected to one input (2) of a gate 2 consisting of an IC of an oven collector TTL. When the voltage of the logic power supply decreases and becomes lower than the voltage of the Zener diode 5, the Zener diode 5 does not shunt the current, so the terminal of the input gate 2 (
2) is held low and its output goes high.

このため入力信号がいかなる動作を行なっても、出力を
ハ、イの状態、すなわち信号なしの状態に保って誤動作
を防止する。この回路のゲート2としては、一般にT 
T L 7438相当を部用し、ツェナーダイオード5
の電圧としては、ゲート2のハイ入力電圧との関係から
なるべく低いものを用いている。
Therefore, no matter what operation the input signal performs, the output is kept in the high or high state, that is, in the absence of a signal, to prevent malfunction. Gate 2 of this circuit is generally T
Using T L 7438 equivalent, Zener diode 5
As the voltage, a voltage as low as possible is used in view of the relationship with the high input voltage of the gate 2.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、別々の電源で動作する装
置本体と入出カドライブとの関係で電源オン・オフに起
因する誤動作を特殊な回路を付加することなく、簡単に
防止することが出来ると共に、確実に誤動作の防止をす
ることができる。
As explained above, the present invention can easily prevent malfunctions caused by power on/off in the relationship between the device main body and the input/output drive, which operate on separate power supplies, without adding a special circuit. At the same time, malfunctions can be reliably prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路図、第2図は従来の信
号出力回路を含む回路図である。図において 1・・・リセット回路、2・・・ゲーI−回路(743
8)、3・・・LSI回路、4.6・・・抵抗、5・・
・ツェナーダイオード、10・・・制御回路、11・・
・インターフェイス回路、12・・・ドライブ装置であ
る。 −°\ 1士 弗 一2/ 第7図 第?図
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram including a conventional signal output circuit. In the figure, 1...reset circuit, 2... game I-circuit (743
8), 3...LSI circuit, 4.6...resistance, 5...
・Zener diode, 10...control circuit, 11...
- Interface circuit, 12...Drive device. −°\ 1 Shifuichi 2/ Figure 7? figure

Claims (1)

【特許請求の範囲】[Claims] オープンコレクタ型ドライバーのゲート回路の一つの入
力に、電源と接地との間に接続したツェナーダイオード
と抵抗との接続回路を接続して構成され、前記ゲート回
路の一方の入力をロウレベルに固定し誤動作を防止した
ことを特徴とする信号出力回路。
The gate circuit of an open collector type driver is configured by connecting a connection circuit consisting of a Zener diode and a resistor connected between the power supply and ground to one input of the gate circuit, and fixing one input of the gate circuit to a low level to prevent malfunction. A signal output circuit characterized by preventing.
JP60147251A 1985-07-03 1985-07-03 Signal output circuit Pending JPS627219A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60147251A JPS627219A (en) 1985-07-03 1985-07-03 Signal output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60147251A JPS627219A (en) 1985-07-03 1985-07-03 Signal output circuit

Publications (1)

Publication Number Publication Date
JPS627219A true JPS627219A (en) 1987-01-14

Family

ID=15426002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60147251A Pending JPS627219A (en) 1985-07-03 1985-07-03 Signal output circuit

Country Status (1)

Country Link
JP (1) JPS627219A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200128750A (en) 2018-07-26 2020-11-16 오리진 바이오테크놀로지 가부시키가이샤 Functional egg and its production method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200128750A (en) 2018-07-26 2020-11-16 오리진 바이오테크놀로지 가부시키가이샤 Functional egg and its production method

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