JPS6273873A - Synchronizing signal separating circuit - Google Patents

Abstract

PURPOSE:To attain stable synchronizing separation output by adopting the constitution that an emitter output is fed to an emitter of a synchronizing separation transistor (TR) so as to change a current discharged during the synchronizing signal period of a charge/discharge capacitor nonlinearly to the synchronizing separation level. CONSTITUTION:In the period of a video signal S3 fed to an input terminal 11, a TR Q21 is turned OFF, a diode D31 and a TR Q22 are turned OFF by the rise in the emitter potential of the TR Q21 and the capacitor C21 is charged by a current I2 of a constant current source I22. In the period of the synchronizing, the TR Q21 is turned ON and the diode D21 and the TR Q22 are turned ON by he descending of the emitter potential of the TR Q21 and an electric charge charged in the capacitor C21 is discharged through the diode D21 and the emitter-collector path of the TR Q21 and a resistor R24. In this case, in selecting the resistor R21, the diode D22 is set not to be turned ON. Thus, a stable synchronizing separation output is obtained.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a synchronization signal separation circuit that can stably separate a synchronization signal from a composite video signal. [Technical Background of the Invention] In general, a synchronization signal separation circuit uses the fact that there is an amplitude axle between a video signal and a synchronization signal included in a composite video signal, and performs synchronization using the cutoff characteristics of a transistor. This is a circuit that extracts signals. A conventional synchronizing signal separation circuit is constructed as shown in FIG. In this circuit, a composite video signal S1 of positive polarity is applied to the input terminal 1;
is connected to the emitter of the NPN transistor Q11 for synchronous separation via a resistor R11, and the input terminal 1 is connected to the emitter of the NPN transistor Q11 for synchronous separation.
12 to the cathode of the diode D11. The base of the transistor Q11 and the anode of the diode D11 are connected in common, and a capacitor C11 is connected between the connection point P1 and the ground point (reference potential point). Further, a current I is generated between the power supply terminal 2 of the direct FE voltage VCC and the connection point P1. A constant 'RvL source 11 is connected, and a resistor R is connected between the collector of the transistor Q11 and the power supply terminal 2.
13 are connected. A synchronous separated output S2 is obtained from the output terminal 3 connected to the collector of the transistor Q11. In the conventional circuit configured as above, the input signal @$1
During the video signal period, the diode D11 and the transistor Q11 are turned off, and the capacitor C11 is charged by the current IO of the constant current source 111. On the other hand, one male of the synchronization signal is connected to the diode D11 and the transistor Q1.
．． is turned on, and the synchronizing signal S2 is taken out from the output terminal 3. Here, the DC amplification factor h[ of the transistor Q11. If hro〉〉1, then during the period of the synchronization signal, the electric charge charged in the capacitor C11 is transferred to the diode D1.
1, and this discharge creates a voltage vth across the resistor R12 that determines the isolation level as shown in FIG.
occurs. Now, let the resistance value of the resistor R and the capacitance value of the capacitor C11 be R and C11, respectively, and when one horizontal line of the input composite video signal (1) (> is T, the time constant R12×011 is T. R12×
011>>Suppose that it is the king. If we consider the positive polarity composite video signal supplied to the input terminal 1 as a pulse waveform as shown in FIG. The voltage generated across the resistor R12 when
Then, the following formula holds true. 1o T = (Vth/R12) ・Ts - (1)
Therefore, Vth-(T/Ts)-R121o-(2). From equation (2), it can be seen that the voltage V (h) that determines the separation level is determined by the ratio of the horizontal period T and the width TS of the synchronizing signal. It's more of a vertical sync signal section.

[Consider the case where it is used to separate the groups.] In domestic television broadcasting in Japan, the width of the vertical signal part is 3 days, and -vertical period]-1 is 2B2.5 days. In other words, the vertical synchronization signal portion during the vertical retrace period is the sixth
It is as shown in the figure. A waveform obtained by integrating the waveform not shown in FIG. 6 is shown in FIG. In the waveform shown in FIG. 7, the amplitude of the vertical synchronizing signal portion relative to the equivalent pulse portion (pedestal portion) is VS. Then, the waveform in Figure 7 is
The isolation level when applied to input terminal 1 in the figure is V thl
Assuming that the width of the vertical synchronizing signal section is Tsl, the following equation holds true using the relationship of equation (2). Vthl = (TI /Ts1) ・R12Io =
・(3) Here, the integration time constant when integrating the composite video signal is selected to be large enough to drop the horizontal synchronization signal component, and the width T31 of the vertical synchronization signal portion is 7sl=2.5.
1. : Select and set R1□Io so that the separation level V thl is separated from the tip of the vertical 11 signal section by 25% of the same II signal width VS, then y th
= 0.25 VS relationship. The vertical 11J signal separation circuit configured as above is as follows:
It is possible to significantly improve vertical synchronization performance during negative ghosting. That is, at the time of negative ghosting, only the vertical synchronization period of the composite video signal drops, making it impossible to extract the vertical synchronization signal using a normal synchronization separation circuit. [Problems with frontal technology] By the way, above we have talked about normal television broadcast signals, but next we will talk about the commercially available VT for preventing dubbing.
Consider the case where a vertical synchronization signal is extracted from a reproduced composite video signal when an R (video tape recorder) tape is reproduced. Figure 8 shows an example of the vertical synchronization signal section of a commercially available VTR tape for preventing dubbing, and the width of the vertical synchronization signal is 0.
．． 51-1. FIG. 9(a) shows a waveform obtained by integrating the waveform of FIG. Considering the case where this waveform is input to input terminal 1 in Fig. 3 and synchronously separated, the equation (3
), Tsl period 2.5H becomes Ts2(-0,5H
), the synchronization separation level V th2 becomes
Vthl in Figure 6 = 0.25VskJtLT, Vt
h2 = 0.25 Vs x (Tsl/Ts2)
= 1.25 Vs, and the separation level V th2 reaches the pedestal portion as shown in FIG. 9 fa). As a result, the output terminal 3 is
) will be taken out, making it impossible to obtain an accurate vertical synchronization separated output. That is, there is a problem in that stable vertical synchronization cannot be achieved, and the reproduced screen may shift or vibrate in the vertical direction. [Object of the Invention] In view of the above-mentioned points, the object of the present invention is to provide a synchronization signal that can be used even when the width of the synchronization signal included in the input composite video signal is narrower than the specified value (the value specified in the vA standard television broadcast signal). It is possible to stably obtain synchronized separated output, and it is also possible to obtain
It is an object of the present invention to provide a synchronization signal separation circuit that can obtain a stable synchronization separation output even when the synchronization signal is disturbed by disturbances such as the above. [Overview of the Invention J The present invention comprises a synchronous separation transistor, a charging/discharging capacitor connected to its base, and a first diode and a resistor connected in series between the base and emitter, In a synchronous signal separation circuit that can set the synchronous separation level by the voltage generated in this resistor during the period,
At the front stage of this circuit, a transistor circuit is provided in which a composite video signal is input to the base of the transistor, the collector is grounded, and the emitter is connected to a constant current source via a resistor.
A second diode is connected from the base of the synchronous isolation transistor to the connection point between the constant current source and the resistor of this circuit, and the emitter output is supplied to the emitter of the synchronous isolation transistor, and the charge/discharge The current discharged during the synchronization signal period of the capacitor is changed non-linearly with respect to the synchronization separation level. [Embodiment 1 of the Invention] Hereinafter, the present invention will be described in detail based on the drawings. FIG. 1 is a circuit diagram showing an embodiment of the synchronization signal separation circuit of the present invention. In this figure, the composite video signal (in the figure, the synchronization signal width is T
s pulse waveform) The input terminal 11 to which S3 is supplied is PN.
The collector of the transistor Q21 is connected to the ground point, and the resistor R21 and the constant current source of the current I are connected between the emitter of the transistor Q21 and the power supply terminal 12 of the DC voltage VCC. 21 are connected in series. The emitter of transistor Q is resistor R
22 to the emitter of the NPN transistor Q22, and the emitters of the transistors 1 to Q21 are connected to the resistor R.
24 to the cathode of the diode D21, the base of the transistor Q and the anode of the diode D21 are commonly connected, and a capacitor C21 is connected between the connection point P2 and the ground point (reference potential point). Further, a constant current source I22 with a current of 1 is connected between the power supply terminal 12 of the DC voltage Vcc and the connection point P2, and a resistor R2 is connected between the collector of the transistor Q22 and the power supply terminal 12.
3 is connected. Furthermore, the anode of a diode D22 is connected to the connection point P2, and the cathode of the diode D2 is connected to the connection point between the constant current source '21 and the resistor R21. A synchronous separated output S4 is obtained from the output terminal 13 connected to the collector of the transistor Q22. In the above configuration, the signal S supplied to the input terminal 11
During the video signal period No. 3, the transistor Q21 is turned off.
Due to the rise in the emitter potential of transistor Q21, diode D21 and transistor Q22 turn off.
The capacitor 4JC21 is charged by a current I of a constant M flow lI22. When the synchronization signal width 1-9 of the signal S3 has a specified value as specified in the standard television broadcast signal, the transistor Q21 is turned on during the period of synchronization I3, and the transistor Q21 is turned on. Due to the drop in emitter potential, diode D21 and l-transistor Q
22 is turned on, and the charge stored in the capacitor C is discharged through the diode D21, the resistor R, and the emitter-collector path of the transistor Q21. At this time, resistance R
A voltage V th3 that determines the isolation level is generated across the resistor R24, and a current 11 flows from the constant M current 1llI21 through the transistor Q to the resistor R21.
If a value of 1 is selected, the diode D22 can be set not to turn on. Using the relationship in equation (2), the following equation is established and reversed. Vth3- (T/TS')・R24I2...(4
) Now, if we consider the case where the circuit of FIG. 1 is used for vertical synchronization signal separation and the waveform shown in FIG. 9(a) is input to the input terminal 11, 'lXR21''0.25 V S
, R21=R24,! : t tL C, resistance R
When the resulting separation level becomes deeper (larger) than 0.25 VS, the cathode potential of diode D22 is lowered and diode D22 is turned on, causing discharge from capacitor C through diode D22. In other words, capacitor C21
The tli electric charge current from 2 changes as shown in Figure 1. When the separation level is 0.25Vs or less, discharge is performed from capacitor C through diode D21, and when the separation level is 0.25Vs or more, discharge is performed through diode D and diode D22, resulting in a discharge flow M. increase(
-It will happen. The total discharge voltage Q1 when the separation level Vth is 0.25VS or less in the waveform shown in FIG. 9(a) is Q −0,
25Vs ; R24X O, 25Ts2-15), and the total discharge charge field 02 where the separation level vth is 0.25Vs or more is calculated by setting the separation level vtb4 as follows: -・(ri holds true. Therefore, the total discharge charge 5Q is, vth4=X-
Let it be VS, but let X>0. 2X −■−1,25 From this formula, X 絢0.77 Therefore, the separation level Vth4 = 0.77 Vs. Therefore, a stable vertical synchronization separated output can be obtained without separating the pedestal section. [Effects of the Invention] As described above, according to the present invention, even when the width of the synchronization signal included in the composite video signal becomes narrower than a specified value, fluctuations in the separation level can be reduced. For example, when reproducing a commercially available VTR tape for preventing dubbing, vertical synchronization signals can be accurately separated. Furthermore, even if the synchronization signal drops due to disturbances such as ghosts, a stable synchronization separation output can be obtained.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the synchronous signal separation circuit of the present invention, Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is a circuit diagram of a conventional synchronous signal separation circuit, and Fig. 4 is a waveform diagram of the positive polarity composite video signal input to the circuit of Figure 3, Figure 5 is a waveform diagram equivalently showing the composite video signal of Figure 4 simplified as a pulse waveform, and Figure 6 is a waveform diagram of the standard composite video signal. FIG. 7 is a waveform diagram showing the vertical synchronizing signal portion of a television broadcast signal. FIG. 7 is a waveform diagram integrating the waveform of FIG. 6. FIG. 8 is a waveform diagram showing an example of the vertical synchronizing signal portion of a commercially available VTR tape. The figure is a waveform diagram showing a waveform obtained by integrating the waveform of FIG. 8 and a synchronization separation output for the integrated waveform. 11...Input terminal 12...Power terminal 13...
Output terminal C21" 22...Transistor R-R
...Resistor C21...Capacitor DD...Diode 1. 1...constant current source

Claims (1)

[Claims] A composite video signal including a synchronizing signal is supplied to the base, the emitter is connected to a predetermined potential point via a first resistor and a first constant current source, and the collector is connected to a reference potential point. a first transistor that conducts during the synchronization signal period; a capacitor that is charged via a second constant current source; an emitter connected to the emitter of the first transistor; a second transistor connected to a predetermined potential point, whose base is supplied with the voltage applied to the capacitor and whose collector extracts a synchronously separated output; the base of the second transistor and the emitter of the first transistor; A first diode and a third resistor are connected in series between the first diode and the third resistor, and the first diode is made conductive during the synchronization signal period to discharge the electric charge of the capacitor, and at the time of this discharge, the third resistor is connected in series. between a connection point between the first constant current source and the first resistor, and the base of the second transistor; the second connected to
a second circuit for discharging the charge of the capacitor by making the second diode conductive in response to a change in the synchronous separation level, thereby making a change in the discharge current of the capacitor non-linear; A synchronous signal separation circuit comprising: