JPS6276571U - - Google Patents
Info
- Publication number
- JPS6276571U JPS6276571U JP16850485U JP16850485U JPS6276571U JP S6276571 U JPS6276571 U JP S6276571U JP 16850485 U JP16850485 U JP 16850485U JP 16850485 U JP16850485 U JP 16850485U JP S6276571 U JPS6276571 U JP S6276571U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- printed pattern
- inner layer
- conductive
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 description 2
Description
第１図はこの考案の一実施例による印刷配線板
の断面図、第２図は従来の印刷配線板の断面図で
ある。
１：基板、２：内層印刷パターン、３：スルホ
ール、４：電子部品の端子、５：半田層、６：非
導電部、７：第２のスルホール、８：外層印刷パ
ターン。なお、図中同一符号は同一又は相当部分
を示す。
FIG. 1 is a sectional view of a printed wiring board according to an embodiment of this invention, and FIG. 2 is a sectional view of a conventional printed wiring board. 1: Substrate, 2: Inner layer printed pattern, 3: Through hole, 4: Terminal of electronic component, 5: Solder layer, 6: Non-conductive part, 7: Second through hole, 8: Outer layer printed pattern. Note that the same reference numerals in the figures indicate the same or equivalent parts.
補正 昭６１．１１．２７
図面の簡単な説明を次のように補正する。
明細書第６頁第７行の「５：半田層」という記
載を削除する。Amendment November 27, 1981 The brief description of the drawing is amended as follows. The description "5: Solder layer" on page 6, line 7 of the specification is deleted.
Claims (1)
に上記内層印刷パターンと非導通な部品端子接続
のための導電性スルホールと、上記基板に内層印
刷パターンと導通され部品端子が接続されない導
電性のスルホールと、上記両スルホールを基板表
面において導通されている外層印刷パターンとか
ら形成されていることを特徴とする印刷配線板。 A substrate having a printed pattern on an inner layer, a conductive through hole on this substrate for connecting a component terminal that is not electrically conductive to the inner layer printed pattern, and a conductive through hole that is electrically conductive to the inner layer printed pattern and to which no component terminal is connected to the substrate. . A printed wiring board, characterized in that both of the above-mentioned through holes are formed from an outer layer printed pattern which is electrically connected on the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16850485U JPS6276571U (en) | 1985-11-01 | 1985-11-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16850485U JPS6276571U (en) | 1985-11-01 | 1985-11-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6276571U true JPS6276571U (en) | 1987-05-16 |
Family
ID=31101435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16850485U Pending JPS6276571U (en) | 1985-11-01 | 1985-11-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6276571U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01118477U (en) * | 1988-02-02 | 1989-08-10 |
-
1985
- 1985-11-01 JP JP16850485U patent/JPS6276571U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01118477U (en) * | 1988-02-02 | 1989-08-10 |
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