JPS6279627A - Reacting method for semiconductor material at high temperature - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention generally relates to a method for reacting surfaces of semiconductor materials at controlled elevated temperatures for short periods of time.

In particular, it relates to methods of forming thin dense oxide layers, thin epitaxial layers and shallow diffusion layers.

BACKGROUND OF THE INVENTION Recent publications have shown the use of short, high temperature anneals to minimize dopant diffusion during post-implantation anneals. The silicon is heated by radiation from light sources including tungsten-halogen lamp arrays, argon discharge lamps, xenon flash lamps, and resistively heated black diodes. These high-temperature light sources can
Silicon can be rapidly heated to temperatures of 1000 to 1200°C.

In E2FROM, a thin oxide is grown over a portion of the drain, followed by the formation of a heavily doped polysilicon floating gate. FIG. 2 shows a portion of a typical device including body 11 and drain 12. FIG. Oxide layer 1 including a thin region 14 in the drain
3 is formed on the surface of the device. A floating gate 16 is formed on the oxide layer 13. The device then includes another oxide layer 17 and an outer gate 18.

In operation, a high electric field is established between the floating gate and the drain, allowing electrons to pass from the drain to the floating gate and vice versa.

The charge sent to the floating gate can modify the threshold voltage during normal operation of the device, thereby allowing the device to be used as a memory element.

Problem that the invention seeks to solve Thin oxides are currently formed by conventionally growing oxides at relatively low temperatures (800'C) to limit their growth to about 1oO has been done. However, when growing oxides at such low temperatures, the oxide properties such as oxide "pinhole" density, electric field at breakdown, and charge trapping density are not optimal for the device. It won't happen. For VLSI devices, dense oxide layers are required.

Increasing the oxidation temperature to 1100°C improves the properties of the oxide layer, but the oxide growth rate is very fast at 1100°C, and conventional oxidation techniques cannot
It is not possible to form oxides with sufficiently controlled thicknesses on the order of 100 required for VLSI devices, MOSFETs, and other semiconductor devices.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for forming oxides of controlled thickness at elevated temperatures.

It is known that the redistribution of impurities during annealing can be controlled by introducing interstitial atoms. Therefore, interstitial atoms of silicon are formed by oxidation. Thus, by precisely controlling the thickness of the oxide layer, the redistribution and diffusion depth of traps during annealing is controlled.

Therefore, another object of the present invention is to control the number of interstitials and thus the diffusion during annealing.
The goal is to form oxides of controlled thickness at elevated temperatures.

According to another feature of the invention, the controlled thickness oxide is doped with impurities as it is grown. The silicon wafer is then rapidly heated and impurities from the oxide diffuse into the wafer's interstitial atoms formed during the oxidation process.

By including a suitable atmosphere in the furnace, rapid thermal cycling is used to effect controlled etching and controlled epitaxial growth.

Yet another object of the invention is to form a controlled oxide;
An object of the present invention is to provide an improved high temperature process for diffusion, etching or epitaxial growth.

The above and other purposes are to rapidly heat a silicon wafer to a high temperature, maintain this temperature for a short period of time, and then cool it by placing the wafer in an atmosphere containing a chemical composition that reacts with the surface of the wafer. This is achieved by a method comprising the steps of:

These and other objects of the present invention will be understood from the following detailed description taken in conjunction with the accompanying drawings.

EXAMPLE It has been found that the oxidation of silicon can be expressed mathematically by the following relationship.

xo”/B + xo/B/A = t
(1) However, is the oxidation time, and xo is,
The oxidation thickness (B/A) is a function of the oxidation temperature T and the silicon crystal direction, and has the following value.

(B/A)=2.7X10'exp(-2,0/kT
) μm/sec (2) This is for silicon with crystal orientation (100).

This is the case when oxidation is carried out in steam.

For thin oxides, the main terms in equation (1) are:

x, / (B / A) = t
(3) Equation 3 can be written as follows.

(dxa/dt)=(B/A)
(4) If the temperature T changes during oxidation, the thickness of the growing oxide satisfies the following equation, dx, /dt=B(T)/A(T)=f,(T)
, (5) and is calculated by explicitly recognizing the dependence of T on .

T= f2(T) , ,
(6) When formula (6) is modified so that L is expressed as a function of T, the following is obtained.

t-q(T) (7) Here, the following equation is obtained.

d t = q'(T) d T
(8) Using formulas (4), (5) and (8), Xl.

is expressed as first order.

Xo”/f, (T)q’(T)dT
(9) T formula (9) is as follows: when the temperature T changes during the oxidation cycle,
The growth of thin oxides can be calculated.

These conditions are of interest because they can be used to achieve precise control to achieve precise oxide growth and precise semiconductor doping.

FIG. 1 schematically shows a radiation furnace 21 with radiation sources 22 and 23 for irradiating a wafer 24. FIG. This furnace has two populations 26 and 27.

Thin oxide growth is precisely controlled by rapid thermal cycles created by irradiating the silicon wafer with an array of quartz halogen lamps or a very bright arc lamp. The temperature profile of such a device is as follows.

The temperature T increases linearly from the ambient temperature Ta based on the following equation.

T-Ta=r1j O<t<tt (10
) The temperature T is then kept constant at the value TP obtained at 1=11 and up to 1=12.

Tp=Ta, +r□t, t, <t<tz (11
) Then, from t2, the temperature T falls linearly at a rate r2 to the second temperature Tb.

T = T p r, t +, z < t <
t3(12)L>2, the temperature T changes over time (t-
tz), but for search purposes such a level of sophistication is not necessary.

During operation, from temperature T'h<0℃, 11
00℃, remained constant at this 1100℃ for 5 seconds, then increased from 1100℃ to 400℃ for 25 seconds.
A temperature profile is used that reduces the temperature to For these values, Ta is 0°C, r is 110°C/s, Tp is 1100°C, r2 is 35°C/s, and T
b is 400°C.

The growth of the corresponding oxide under steam oxidation conditions is calculated by the following formula:

Xo” x,, + XO2+ Xl+3
(13) However, xo1= / (2,7xlO4/110) eXp
(-2/kT)dT (14) = 8.44 people x, 2 = [2,7XIO'exp (-2/+h137
3)] $5 (15) = 63.5 people) (,3: f (2,7xlO'/35) eXp
(-2/kT)ciT (16) = 26.5 people Therefore, a total oxide thickness of 98.4 people is grown. By varying both the peak temperature in the rapid thermal anneal and the time at this peak temperature (tz ti), other controlled thin oxide thicknesses can be optionally grown. Also, using dry oxygen instead of steam,
The pre-exponential coefficient in (B/A) is 2.7 x 10
It can be reduced from 'μm/sec to 1.03×103 μm/sec to obtain an oxide thickness that is 26 times smaller under the same temperature conditions. Thus, a technique is provided for growing controllable thin oxide layers on silicon substrates through rapid thermal cycling.

VLS I where gate oxide thickness of about 100 is desired
As an example of how to apply this method to a device, the third
A silicon substrate 31 is shown in the figure, on which a thick (field) oxide 32 is grown by conventional processing, and this oxide is deposited using conventional photolithographic techniques in the regions 33 in which the FET is to be formed. has been removed by. The substrate is then subjected to an oxidation cycle as described above and a 98.4 gate oxide 34 is grown.

A layer of polysilicon 36 is then deposited over the entire structure and contoured to form a gate layer 37 for the MOSFET. The gate oxide is then removed from the exposed areas and the gate is doped using an arsenic implant 38 and an anneal, with simultaneous source, drain and gate doping. The previously contoured gate layer 37 is self-aligned with the source and drain regions. This is important when applied to VLSI.

Using a controlled oxidation cycle as described above, the redistribution of impurities during annealing is precisely controlled. This is because interstitial atoms of silicon are generated by oxidation.
For example, the diffusion coefficient of arsenic at a density level of 101"/Cm3 is improved by approximately 50%. Therefore, the third
If the arsenic-implanted structure shown in the figure is to be annealed in vacuum at a low temperature (e.g., 700'C) to repair large crystal damage, the rapid oxidation cycle described above can be used. By growing a 100% oxide on top of the implanted crystalline regions described above, arsenic redistribution can be precisely controlled. Here, accurate control over oxide thickness means:
This implies the release of a precisely controlled small number of silicon interstitial atoms during oxidation, which leads to a strict restriction of arsenic diffusion during electrical activation at 1100°C.

This is of great importance because the area at the posterior end of the arsenic implanted area is
This is because it is desirable to diffuse the arsenic just through areas where misalignment loops or other defects may occur during annealing.

Doped oxides can also be grown by simply including a doping gas in the oxidation atmosphere during the oxidation cycle to obtain controlled thickness. Therefore.

For example, if phosphine (PH3) can be poured into a reaction tube, the following chemical reaction will first occur: 2PH3+402→P2O5+3H20 (17) Then, a first-order reaction will occur on the silicon surface.

2P20. +53i (solid) -+4P+5Sio2
(18) Here, Sio□ is generated and phosphorus is released, doping into the 100 μm thick oxide and slightly diffusing into the silicon surface.

After this reaction is finished, remove the oxidizing atmosphere.

Alternatively, for example, dry flowing nitrogen N2 can be used followed by a second rapid thermal cycle to diffuse the phosphorus from the dope gas into the silicon to precisely controlled depths. For example, the exact same thermal cycle used for oxidation will diffuse phosphorus to a depth of about 500 nm into the underlying silicon substrate.

Yet another example of a typical process is to start the process with a silicon wafer and a gas stream consisting of N2, H, and C1. A rapid thermal cycle with a peak temperature of 800°C is used to controllably etch the silicon surface, remove residual oxides and contaminants from the surface, and prepare the surface for epitaxial growth. HC is then removed from the device at a low temperature.
purge the gas stream to either 5iC14+hydrogen or pure 5i
Switch to either H1. Silicon is epitaxially grown on the substrate at a rate of about 1 μm/min using rapid thermal cycling to reach a peak temperature of 1200°C. Here, if the reaction is carried out for 6 seconds, a silicon epitaxial layer with a thickness of 100 layers is grown. This layer is
As in conventional epitaxial reactions, doping is achieved by including a dopant in the gas stream.

Thus, the rapid thermal process described above provides a technique for growing five layers in a controlled manner, which can be extended to layer thicknesses on the order of 100 layers. By growing a large number of npnpFJs in this manner, structures that could previously only be formed using very expensive molecular beam epitaxial techniques can be created.

Additionally, using a rapid thermal cycling process.

Controlled growth to a thickness of about 50A.

A to G a A s using G a Cl 3 and arsenic
, H4 can also be attached. It is also possible to perform epitaxial growth on a GaAs substrate, or to grow polycrystals on a substrate with an inappropriate lattice constant (e.g., growing a fine-grained polycrystalline layer on an amorphous substrate such as quartz). ). As with silicon, these layers are doped by including appropriate gases in the growth stream.

Thus, an improved method for controlling surface reactions such as oxide growth, impurity diffusion, etching, and crystal growth has been provided.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a radiant heating device with a gas inlet and outlet and in which a wafer is installed; FIG.
A partial diagram of the 2F ROM and Figure 3 are VLSI (7
) is a partial diagram showing a FET made in a MO8FET circuit. 11...Main body 12...Drain 13...
Oxide layer 14... Thin region 16... Floating gate 17... Oxide layer 18... External gate 21...
・Radiation furnace 22.23...Radiation source 24...Wafer 31...Silicon substrate 32.
...Oxide 34...Gate oxide 36...Polysilicon layer 37...Gate layer 38...Arsenic implantation procedure amendment (method) 61.2.1! li Month, Day 1, Showa 1985, Incident Display 1985 Patent Case No. 217763
No. 2, Title of the Invention: Method for Reacting the Surface of a Semiconductor Material at High Temperatures 3, Relationship with the Amendment Case Applicant Name: James F. Kibans 4, Agent Address: 3-3-1 Marunouchi, Chiyoda-ku, Tokyo Telephone (main) 21! -87412114. -・Name (59
95) Patent Attorney Minoru Nakamura ε5ノ11'

Claims (16)

[Claims] (1) A method of forming one or more very thin films on a substrate, the method controlling the formation of the very thin films to a uniform thickness in a predetermined atmosphere with a selected reactant. , rapidly heating the substrate and linearly increasing the temperature of the atmosphere at a first rate to a predetermined temperature, and increasing the temperature of the atmosphere for a selected number of seconds.
maintaining said elevated temperature and cooling said substrate in the presence of a selected reactant;
A method characterized in that the temperature is linearly reduced at a second rate to a relatively low temperature. (2) The above-mentioned atmosphere is an oxidizing atmosphere that forms an oxide on the surface of the semiconductor material.
The method described in section. (3) The method according to claim (2), wherein the oxidizing atmosphere contains impurities, and an oxide is formed at the same time as the impurities are diffused. (4) The method of claim (1), wherein the selected reactants are N_2 and HCl. (5) A method according to claim (1), wherein the atmosphere contains atoms of a semiconductor material to effect epitaxial growth. (6) The semiconductor material is silicon, and the atoms are:
The method according to claim (5), wherein the atom is a silicon atom. (7) The method according to claim (6), wherein the silicon atoms are SiCI_4. (8) The method according to claim (6), wherein the silicon atoms are SiH_4. (9) A method according to claim (1), wherein the substrate is heated by pulsed radiation. (10) The above predetermined temperature is approximately 1000°C to 1200°C.
A method according to claim 1, wherein the relatively low temperature is approximately 400°C. (11) The method according to claim (1), wherein the predetermined temperature is maintained for about 5 seconds. 12. The method of claim 1, wherein said selected reactants are placed in the same atmosphere or environment used to raise and lower the temperature of said wafer. (13) Each of the very thin films has a thickness of about 500 Å.
A method as claimed in claim (1), wherein the thickness is less than or equal to. (14) The method of claim (1), wherein the selected reactants are phosphine and nitrogen. (15) Claim (1) in which an epitaxial layer of silicon is grown to form a very thin film.
The method described in section. (16) The above selected reactants include nitrogen and HCl,
The method according to claim 15, which is SiCl_4 and hydrogen or pure SiH_4.