JPS6281227U - - Google Patents
Info
- Publication number
- JPS6281227U JPS6281227U JP17192285U JP17192285U JPS6281227U JP S6281227 U JPS6281227 U JP S6281227U JP 17192285 U JP17192285 U JP 17192285U JP 17192285 U JP17192285 U JP 17192285U JP S6281227 U JPS6281227 U JP S6281227U
- Authority
- JP
- Japan
- Prior art keywords
- address
- signal
- photocoupler
- outputs
- setting section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Power Sources (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は従来例のブロツク図である。
１……マイクロコンピユータ、２，３……イン
タフエイス回路、４……アドレス選択信号デコー
ダ、５……フオトカプラ供給電源切替回路、６…
…ゲート回路、７……フオトカプラ、８……外部
リレー接点、９……アドレス設定部、１０……ア
ドレス信号線、１１……データ入力用信号線。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a block diagram of a conventional example. DESCRIPTION OF SYMBOLS 1...Microcomputer, 2, 3...Interface circuit, 4...Address selection signal decoder, 5...Photocoupler supply power switching circuit, 6...
... Gate circuit, 7 ... Photocoupler, 8 ... External relay contact, 9 ... Address setting section, 10 ... Address signal line, 11 ... Data input signal line.
Claims (1)
カプラと、アドレス設定部と、マイクロコンピユ
ータからのアドレス信号が前記アドレス設定部の
アドレスと一致したときのみ一致信号を出力する
デコーダと、前記一致信号に応じて前記接点の状
態を前記フオトカプラを介して前記マイクロコン
ピユータにデータ信号として出力するゲート回路
とを具備するインタフエイス回路において、前記
一致信号が発生したときのみ前記フオトカプラに
電源を供給する切替回路を具備することを特徴と
するインタフエイス回路。 a plurality of photocouplers each coupled to a plurality of contacts; an address setting section; a decoder that outputs a match signal only when an address signal from a microcomputer matches an address of the address setting section; The interface circuit includes a gate circuit that outputs the state of the contact as a data signal to the microcomputer via the photocoupler, and a switching circuit that supplies power to the photocoupler only when the coincidence signal is generated. An interface circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17192285U JPS6281227U (en) | 1985-11-08 | 1985-11-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17192285U JPS6281227U (en) | 1985-11-08 | 1985-11-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6281227U true JPS6281227U (en) | 1987-05-23 |
Family
ID=31107995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17192285U Pending JPS6281227U (en) | 1985-11-08 | 1985-11-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6281227U (en) |
-
1985
- 1985-11-08 JP JP17192285U patent/JPS6281227U/ja active Pending
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