JPS6281765A - Method for manufacturing silicon carbide devices on silicon substrate - Google Patents

Method for manufacturing silicon carbide devices on silicon substrate

Info

Publication number
JPS6281765A
JPS6281765A JP60222955A JP22295585A JPS6281765A JP S6281765 A JPS6281765 A JP S6281765A JP 60222955 A JP60222955 A JP 60222955A JP 22295585 A JP22295585 A JP 22295585A JP S6281765 A JPS6281765 A JP S6281765A
Authority
JP
Japan
Prior art keywords
sic
substrate
silicon
silicon carbide
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60222955A
Other languages
Japanese (ja)
Other versions
JPH0644569B2 (en
Inventor
Yutaka Hayashi
豊 林
Yasushi Kondo
康司 近藤
Tetsuo Takahashi
徹夫 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60222955A priority Critical patent/JPH0644569B2/en
Publication of JPS6281765A publication Critical patent/JPS6281765A/en
Publication of JPH0644569B2 publication Critical patent/JPH0644569B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は高温動作が可能な炭化シリコン(SiC)デバ
イスの製造方法に関し、特にシリコン(Si)基板上に
成長させたSiCを用いたSiCデバイスの製造方法に
関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a silicon carbide (SiC) device capable of high-temperature operation, and particularly to a method for manufacturing a silicon carbide (SiC) device that is capable of high-temperature operation, and in particular, an SiC device using SiC grown on a silicon (Si) substrate. Relating to a manufacturing method.

[従来の技術] SiCは高温での動作が可能な半導体である。[Conventional technology] SiC is a semiconductor that can operate at high temperatures.

SiCをSi基板上に成長させる技術は近年とみに発展
し、例えば面方位(100)のSi基板上に5iHaと
Z38Bを用いて化学気相成長法により、SiCを5〜
iopm成長させることが可能になっている。しかしS
i基板とSiCとの熱膨張係数の差および格子Si基板
を溶解して得たSiC薄片で行われなければなら・ない
という不便があった。
The technology for growing SiC on a Si substrate has developed rapidly in recent years. For example, SiC can be grown on a (100) Si substrate by chemical vapor deposition using 5iHa and Z38B.
It has become possible to grow iopm. However, S
There were inconveniences such as the difference in thermal expansion coefficient between the i-substrate and SiC and the necessity of using a SiC thin slice obtained by melting the lattice Si substrate.

また絶縁層としてSiC表面を酸化して得られる5i0
2膜を利用する場合、SiCの酸化速度がSiに比べて
非常に遅く、十分な厚さの5i02膜が得にくいので、
MOS )ランジスタその他のデバイスが作製し難いと
いう欠点があった。
In addition, 5i0 obtained by oxidizing the SiC surface as an insulating layer
When using two films, the oxidation rate of SiC is very slow compared to Si, and it is difficult to obtain a 5i02 film of sufficient thickness.
The drawback was that it was difficult to manufacture transistors (MOS) and other devices.

[発明が解決しようとする問題点] 本発明は、このようなSi基板上に成長させたSiCに
生じ易いクラックの発生を防止し、また電気的特性評価
やデバイス作製に必要な配線の絶縁、デバイスのアイソ
レーションに必要な絶縁のソ基板上に炭化シリコン層を
成長させ、成長させ覧炭化シリコン層の一部を除去して
シリコン基板の表面を露出させ、残された炭化シリコン
層の表面および露出されたシリコン基板の表面に酸化シ
リコン膜を形成し、シリコン基板上の酸化シリコン膜を
残された炭化シリコン層に形成するデバイスの配線のた
めの絶縁層とすることを特徴とする。
[Problems to be Solved by the Invention] The present invention prevents the occurrence of cracks that are likely to occur in SiC grown on such a Si substrate, and also improves the insulation of wiring necessary for electrical property evaluation and device fabrication. A silicon carbide layer is grown on the insulating substrate required for device isolation, and a portion of the silicon carbide layer is removed to expose the surface of the silicon substrate, and the surface of the remaining silicon carbide layer and The method is characterized in that a silicon oxide film is formed on the exposed surface of the silicon substrate, and the silicon oxide film on the silicon substrate is used as an insulating layer for wiring of a device to be formed on the remaining silicon carbide layer.

[作用] 本発明によれば、Si基板上にセルファライン的の良好
な絶縁を確保することができる。
[Function] According to the present invention, good self-alignment insulation can be ensured on the Si substrate.

いた化学気相成長法によって、Si0層20を0.5g
m程度の厚さを成長させる(第1図(A) ) 。
0.5g of Si0 layer 20 was deposited by chemical vapor deposition method.
The film is grown to a thickness of about 1.0 m (Fig. 1(A)).

次にSiC層上にフォトレジストによるマスクを設け、
フロンおよび酸素によるプラズマエツチングを行って必
要な形状および個数のSiCの島を残してSiC層を除
去する(第1図(B))、図には便宜上1個の島のみを
示す。
Next, a photoresist mask is provided on the SiC layer,
Plasma etching using freon and oxygen is performed to remove the SiC layer leaving SiC islands of the required shape and number (FIG. 1(B)); only one island is shown in the figure for convenience.

次に水蒸気雰囲気中で1150°C約30分加熱し。Next, it was heated at 1150°C for about 30 minutes in a steam atmosphere.

熱酸化を行う(第1図(C))、この酸化によって形成
される5i02膜11の厚さはSiC20上では約0.
05gmであるが、Si 10上ではその約10倍の0
.55 pLmに達する。
Thermal oxidation is performed (FIG. 1(C)), and the thickness of the 5i02 film 11 formed by this oxidation is approximately 0.0 mm on SiC 20.
05gm, but on Si 10 it is about 10 times that
.. Reaching 55 pLm.

う1ンジスタ、集積回路などを設けたSiCデバイスを
容易に製造することができる。
SiC devices provided with transistors, integrated circuits, etc. can be easily manufactured.

こうしてSi基板上に設けたSiCをn層とするMOS
FETを作製する例を第2図(A)ないしくE)を参照
して説明する。第1図(C)に示したSiCを用い、表
面のS i02層をSiC20の表面が露出するまで1
例えば(NH4F +HF)液を用いてエツチングし除
去する(第2図(A))。
A MOS with an n-layer of SiC provided on a Si substrate in this way
An example of manufacturing an FET will be described with reference to FIGS. 2(A) to 2(E). Using the SiC shown in FIG.
For example, it is removed by etching using a (NH4F +HF) solution (FIG. 2(A)).

露出されたSiC上およびSi基板上のS i02の上
に、例えばSiH4の熱分解による化学気相成長法によ
って、多結晶Si層3oを0.5ルm厚程度成長させる
(第2図(B))、この時多結晶Si層30にはSiC
20に対してアクセプタとなる不純物、例えばAfLを
添加しておく。
A polycrystalline Si layer 3o is grown to a thickness of about 0.5 μm on the exposed SiC and Si02 on the Si substrate by, for example, chemical vapor deposition using thermal decomposition of SiH4 (see Fig. 2(B)). )) At this time, the polycrystalline Si layer 30 contains SiC.
An impurity serving as an acceptor, for example, AfL, is added to 20.

次に多結晶Si層30をソースおよびドレイン電極とし
て用いるため、多結晶Si 30のゲート電極にヲ1 一相当する部分その他不要部分を除去する(第2図゛、
1 1IC) )、多結晶Siの除去は、腐食剤として例え
ば暑 い、  5i02膜31を形成する(第2図(D))、
形成されたS i02膜31の厚さは多結晶Si 30
の上では約0.5 grn 、  SiC20の上では
約400人である。
Next, in order to use the polycrystalline Si layer 30 as a source and drain electrode, the portion of the polycrystalline Si layer 30 corresponding to the gate electrode and other unnecessary portions are removed (see Fig. 2).
1 1IC)), the removal of polycrystalline Si is carried out using, for example, hot water as a corrosive agent, forming a 5i02 film 31 (Fig. 2(D)),
The thickness of the formed Si02 film 31 is that of polycrystalline Si30
It is about 0.5 grn on SiC20 and about 400 grn on SiC20.

先に多結晶Si 30中に添加しておいた不純物はこの
熱酸化中にSiC中に拡散してソースおよびドレイン領
@51 、52が形成される。  5i02膜31のう
ちSiC20の上の薄い部分はゲート絶縁膜として、多
結晶Si 30の上の厚い部分は、後に形成するゲート
金属等の電極に対する絶縁層として用いられる。
The impurities previously added to the polycrystalline Si 30 are diffused into the SiC during this thermal oxidation to form source and drain regions @51 and 52. The thin part of the 5i02 film 31 above the SiC 20 is used as a gate insulating film, and the thick part above the polycrystalline Si 30 is used as an insulating layer for an electrode such as a gate metal that will be formed later.

多結晶5i30.30の一上部の5i02膜31に、C
F。
C on the 5i02 film 31 on top of the polycrystalline 5i30.
F.

を用いたプラズマエツチングあるいは(NH4F +H
F)液を用いた湿式エツチングなどによってコンに却下
してソース電極41(43)、ドレイン・電極43(4
1)、ゲート電極42として、PチャネルMO3FET
が完成する(第2図(E))。
Plasma etching using (NH4F +H
F) The source electrode 41 (43) and the drain electrode 43 (43) are completely removed by wet etching using a liquid.
1), P-channel MO3FET as gate electrode 42
is completed (Figure 2 (E)).

一方5i07膜31を形成する工程(第2図(0))に
おいて、 1000℃以下の低温で絶縁膜を形成した場
合は多結晶5130中に添加しておいた不純物はSiC
中へは殆んど拡散せず、むしろ多結晶Si 30はSi
Cとオーム性接触を示すので、上記一連の製造工程によ
りnチャネルのMOSFETを形成することができる。
On the other hand, in the step of forming the 5i07 film 31 (FIG. 2 (0)), if the insulating film is formed at a low temperature of 1000°C or less, the impurity added to the polycrystalline 5130 will be
There is almost no diffusion into the interior, rather polycrystalline Si 30 is Si
Since it exhibits ohmic contact with C, an n-channel MOSFET can be formed through the series of manufacturing steps described above.

第2図において、S1基板上に成長させたSiCにPチ
ャネルとに09FETを形成した例を示したが、本発明
のSiCデバイスはこの例に限られるものではない。
Although FIG. 2 shows an example in which a P-channel and 09FET are formed on SiC grown on an S1 substrate, the SiC device of the present invention is not limited to this example.

[発明の効果] 以上説明したように、Si基板上に成長させた一−Si
Cの一部をエツチングによって除去した後に
[Effect of the invention] As explained above, -Si grown on a Si substrate
After removing part of C by etching

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)ないしくC)は本発明の詳細な説明する部
分断面図、 第2図(A)ないしくE)は本発明を用いてMOSFE
Tを作成する例を示す部分断面図である。 10・・・Si基板、 11 、31・・・5102. 20・・・SiC, 30・・・多結晶S1. 41・・・ソース(ドレイン)電極、 42・・・ゲート電極、 43・・・ドレイン(ソース)電極、 51・・・ソース(ドレイン)、 第1図
1(A) to C) are partial cross-sectional views explaining the present invention in detail, and FIG. 2(A) to E) are MOSFEs using the present invention.
It is a partial sectional view showing an example of creating T. 10...Si substrate, 11, 31...5102. 20...SiC, 30...Polycrystalline S1. 41... Source (drain) electrode, 42... Gate electrode, 43... Drain (source) electrode, 51... Source (drain), Fig. 1

Claims (1)

【特許請求の範囲】 炭化シリコン層を成長させたシリコン基板において、前
記成長させた炭化シリコン層の一部を除去して前記シリ
コン基板の表面を露出させ、 残された前記炭化シリコン層の表面および前記露出され
たシリコン基板の表面に酸化シリコン膜を形成し、 前記シリコン基板上の酸化シリコン膜を前記残された炭
化シリコン層に形成するデバイスの配線のための絶縁層
とすることを特徴とするシリコン基板上の炭化シリコン
デバイスの製造方法。
[Claims] In a silicon substrate on which a silicon carbide layer has been grown, a portion of the grown silicon carbide layer is removed to expose the surface of the silicon substrate, and the surface of the remaining silicon carbide layer and A silicon oxide film is formed on the exposed surface of the silicon substrate, and the silicon oxide film on the silicon substrate is used as an insulating layer for wiring of a device to be formed on the remaining silicon carbide layer. A method for manufacturing silicon carbide devices on a silicon substrate.
JP60222955A 1985-10-07 1985-10-07 Method for manufacturing silicon carbide device on silicon substrate Expired - Lifetime JPH0644569B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60222955A JPH0644569B2 (en) 1985-10-07 1985-10-07 Method for manufacturing silicon carbide device on silicon substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60222955A JPH0644569B2 (en) 1985-10-07 1985-10-07 Method for manufacturing silicon carbide device on silicon substrate

Publications (2)

Publication Number Publication Date
JPS6281765A true JPS6281765A (en) 1987-04-15
JPH0644569B2 JPH0644569B2 (en) 1994-06-08

Family

ID=16790494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60222955A Expired - Lifetime JPH0644569B2 (en) 1985-10-07 1985-10-07 Method for manufacturing silicon carbide device on silicon substrate

Country Status (1)

Country Link
JP (1) JPH0644569B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008510316A (en) * 2004-08-16 2008-04-03 マイクロン テクノロジー インコーポレイテッド Low dark current image sensor with epitaxial SIC and / or carbonized channels for array transistors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS547883A (en) * 1977-06-20 1979-01-20 Nec Corp Semiconductor device and its manufacture
JPS59155943A (en) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS547883A (en) * 1977-06-20 1979-01-20 Nec Corp Semiconductor device and its manufacture
JPS59155943A (en) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008510316A (en) * 2004-08-16 2008-04-03 マイクロン テクノロジー インコーポレイテッド Low dark current image sensor with epitaxial SIC and / or carbonized channels for array transistors

Also Published As

Publication number Publication date
JPH0644569B2 (en) 1994-06-08

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