JPS628213A - Function generation circuit - Google Patents

Abstract

PURPOSE:To decrease the memory capacity of a table type function generating circuit by generating a function output and difference data corresponding to input data in each specific period from the 1st and the 2nd memories and adding two memory outputs together. CONSTITUTION:The 1st memory 1 generates function outputs f(X0), f(X1)... which vary at intervals DELTA of X for input data X and the 2nd memory 2, on the other hand, generates a difference output DELTA(X) corresponding to the function output. The 1st memory outputs 16-bit function data f(X0) as D1 for optional input data X=Xa and the 2nd memory outputs 8-bit positive/negative difference data DELTAf(Xa) as D2. A sign byte 3 generates an 8-bit output D3 of '0's or '1's according to the MSB output of the data D2 is 1 or 0 and it becomes the high- order bits of the data D2, which are applied to an adder 4 as 16-bit data output corresponding to the difference data DELTAf(Xa) and added to the data D1, thereby generating a function data output.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to reducing memory capacity in a table-based function generation circuit using memory.

(Prior Art) FIG. 3 is a block diagram showing an example of a table-type function generation circuit using a conventional memory.

A memory 10 consisting of RAM, ROM, etc. receives input data X.
The address of the function output data f(×) is specified by
to occur.

(Problems to be Solved by the Invention) However, if the number of bits of input data is n and the number of bits of output data is 1, the required memory capacity ff1c becomes C-2n-1. For example, in the case of n-16°1-16, the number of C-2 words is 6.16-128KB, which requires a large memory.

The present invention has been made to solve the above problems, and an object of the present invention is to realize a table-type function generation circuit that can reduce the memory container.

(Means for Solving the Problem) The present invention relates to a function generation port/path that generates predetermined function output data in response to input data. a first memory that generates function output data corresponding to each input data at predetermined intervals, and a first memory whose address is specified by the input data and which corresponds to the function output and the input data at predetermined intervals; a second memory that generates an output corresponding to the difference in bits with a smaller number of bits than the first memory output; and an adder that adds the first memory output data and the second memory output data. The point is that the device is configured to generate function output data.

(Operation) According to the function generating circuit configured as described above, a function output corresponding to input data at predetermined intervals is generated from the first memory, and a function output corresponding to input data within the predetermined interval is generated from the second memory. The above objective can be achieved by generating differential data for , and adding the two memory outputs using an adder.

(Example) The present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of a function generating circuit according to the present invention. 1 is the 16-KB first memory tVI+, which is addressed by data A1 consisting of -H+/13 bits of 16-bit input data (2'6・8 bits-)6
The 4KB second memory M2.3 stores the MSB (Most 51gn1fi) of the output data D2 of this second memory 2.
cant 3ft) Sign byte S to which output OM connects
.

4 is the 16-bit output data D1 of the first memory 1.
．． This is a 16-bit adder that connects the 8-bit output data D2 of the second memory 2 and the 8-bit output data D3 of the 11th code byte 3 to generate a 16-bit function output f(X). .

The operation of the apparatus configured as described above will be explained below using the operation explanatory diagram of FIG. f(x) is a function to be realized here and satisfies the following condition indicating smoothness.

For input data (X+), f(X
2), ... is generated. On the other hand, the second memory stores the function output r(Xo) of the function f(x) for the input data X,
Generates a differential output Δf (x) for f (X+ >, f (X2), =. Any input data X-X
For @, the first memory 1 stores the function data f(Xo) as Dl
The second memory 2 outputs the positive/negative difference data Δf(Xs) as 02 in 8 bits (negative data is expressed in 1's complement). Code byte 3 generates an 8-bit output D3 of oooooooooo when the MSB output of data D2 is 0, and 11111111 when the MSB output of data D2 is 1. Data D3 is combined with data D2 to become its upper bit, and the difference data Δf(
Xa) becomes a 16-bit data output and is applied to the adder 4. Since the adder 4 adds the 16-bit output data D1 of the first memory 1 to the other input, the result is the sum of the function data f (Xo) and the difference data Δf(Xa), or f(Xa). corresponding 16
Generates a 111I number data output of bits.

According to a device with such a configuration, the required memory capacity is 2
” (16/2 + 8) -80KB, which is a significant reduction compared to the conventional method's 216.16-128KB.

In general, in a function generation circuit where the number of bits of input data is n1 and the number of bits of output data is 1, the smoothness of the function to be realized is If'(x + ΔX) - f (X ) I<2”
When the condition (m < l) is satisfied, the number of bits of the address input of memory 1 is set to n-T, and the number of bits of the output data of memory 1 is set to 1.
1 The number of bits of the address input of memory 2 is n, and the number of bits of the address input of memory 2 is
If the number of bits of output data is m, then the memory capacity ff
1C becomes C-2''<m+l/2''), and when T is large and the difference between m and 1 is large, a large reduction effect can be obtained.

(Effects of the Invention) As described above, according to the present invention, a table-type function generation circuit that can reduce memory capacity can be realized with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of the function generating circuit according to the present invention, FIG. 2 is an operational explanatory diagram for explaining the operation of the device shown in FIG. 1, and FIG. 3 is a diagram of the conventional function generating circuit. FIG. 2 is a block configuration diagram showing the configuration. 1... first memory, 2... second memory, 4...
-Adder, X...Input data N f (X)...Function output data.

Claims (1)

[Claims] In a function generation circuit that generates predetermined function output data in response to input data, a first memory that is addressed by the upper bits of the input data and generates corresponding function output data for each input data at a predetermined interval; a second memory that is addressed by the input data and generates an output corresponding to the difference between the function output and the function output corresponding to the input data at predetermined intervals in a smaller number of bits than the first memory output; and an adder for adding the first memory output data and the second memory output data, and is configured to generate function output data from the adder.