JPS628228A - Method and device for digital signal processing - Google Patents

Abstract

PURPOSE:To process many kinds of digital signals efficiently with ease by using an input/output memory and a memory for internal state variable storage and combining specific program modules. CONSTITUTION:Instructions of respective program modules stored in a corresponding program memory 103 are accessed successively with block commands stored in a block command memory 101. State variables and input variables necessary for the accessed program modules are read out of data in a state variable memory 105 and data in a channel variable memory 107 indicated in a block command and processed successively. Then, processing results are outputted to the channel variable memory 107 specified in the block command. This operation is repeated to perform signal processing.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a digital signal processing method and apparatus thereof, particularly a digital signal processing method for implementing a digital communication terminal station, an audio input/output device, a real-time measuring device, etc. The present invention relates to a processing method and apparatus.

(Prior art and its problems) In order to realize a real-time digital signal processing device by software control, it is necessary to use a high-speed arithmetic unit, a read-only memory for storing data, or a read-only memory for storing instructions that can be read and written. A one-chip LSI called a signal processor was created and is used in various fields.

The signal processor uses a microprogram control system capable of high-speed processing in order to emphasize real-time performance, and by changing the microprogram by t%, fine arithmetic control can be performed. However, on the other hand, it is extremely difficult to create microprograms that maximize execution efficiency, and requires a lot of development man-hours.

For this purpose, a blockraming language translation system (compiler) was created to generate microprograms that could use the programming languages used in ordinary computers. Proceedings of the 24th National Conference of the Information Processing Society of Japan P255-P256
, Ikezaka et al. reported on an optimization method for a prototype compiler for signal processors.

However, optimization of microprograms is generally difficult even with computers, and the execution efficiency of microprograms generated by high-level programming language translation systems such as those shown above is still sufficient, so they are fast. It is difficult to create a program that can be used at a practical processing speed in a signal processor that requires high performance.

Furthermore, since high-level programming languages themselves are not created to describe digital signal processing algorithms, it is not easy to create devices that require large-scale digital signal processing operations using high-level programming languages.

(Object of the Invention) The object of the present invention is to combine a program module that executes a basic digital signal processing algorithm prepared in advance using memory for input/output and memory for storing internal state variables. It is therefore an object of the present invention to provide a general-purpose digital signal processing method and device that can efficiently and easily implement various digital signal processing methods and devices.

(Structure of the Invention) According to the first invention, a program memory stores a plurality of signal processing program modules; a state variable memory stores state variables used during operation of the signal processing program modules stored in the program memory; A channel variable memory for storing input variables and output variables of each of the program modules stored in the program memory, a start address of each of the program modules stored in the program memory, and a start of the state variable memory used by the program module. B includes a block command memory that is used by the program module and stores a block command consisting of a start address of an input variable to the channel variable memory and a start address of the output variable, and an arithmetic processing unit; The stored block commands call the instructions of each of the program modules stored in the corresponding program memory, and state variables and input variables necessary for the called program modules are specified in the block commands. Signal processing is performed by repeating the operation of reading data in the state variable memory and data in the channel variable memory, processing them sequentially, and outputting the processing results to the channel variable memory specified in the block command. A digital signal processing method characterized by the following is obtained.

Further, according to the second invention, there is provided an arithmetic processing unit that performs arithmetic processing, a state variable memory connected to the arithmetic processing unit, a state variable pointer that specifies an address of the state variable memory, and a state variable pointer connected to the arithmetic processing unit. an input channel pointer and an output channel pointer that specify addresses in the channel variable memory; and at least one of the input channel pointer and the output channel pointer is set to the address of the channel variable memory. a selection circuit connected to the arithmetic processing section, the state variable memory, the state variable pointer, the channel variable memory, the input channel pointer, the output channel pointer, and the selection circuit; a memory, a program counter that specifies an address of the program memory, a block command memory that supplies m data to the program counter, the state variable pointer, the input channel pointer and the output channel pointer, and an address of the block command memory. A digital signal processing device is obtained, characterized in that it includes at least a block program counter that specifies a block program counter.

(Operation/Principle of the Invention) In the present invention, since many digital signal processing devices are combinations of basic signal processing algorithms such as digital filters and fast Fourier transform, the signal processor can efficiently perform the basic signal processing algorithms. A program module to be executed automatically is prepared and stored in advance in the program memory. Along with this, the above,
When connecting and using program modules, a channel variable memory is prepared to store input/output data of the program modules in order to transfer necessary data between the program modules. The area starting from the designated address of this channel variable memory is determined as the input/output area of the program module.

Furthermore, a state variable memory is prepared to store data used as state variables within the program module. The area starting from the designated address of this state variable memory is defined as the state variable area of the program module. The present invention allows the program module to be treated as a general-purpose module by combining the program module, the address of the channel variable memory, and the address of the state variable memory into one signal processing instruction. It makes it easier.

(Embodiment) Next, an embodiment of the digital signal processing blade 5m and its device according to the present invention will be described in detail with reference to FIGS. 1 to 6. FIG. 1 shows a configuration diagram of an embodiment of the present invention, which includes a block command memory 101, a block program counter 102, a program memory 103, a program counter 104, a state variable memory 105,
State variable pointer 106 and channel variable memory 10
7, selection circuit 108, and input channel pointer 10
9, output channel pointer 110, and arithmetic processing
111, input boat 112, and output boat 11
It consists of 3.

Each word of the block command memory 101 has an operation field 10II and a state variable field 101.
'2, an input channel field 1013, and an output channel field 1014.

It is assumed that a plurality of program modules commonly used in digital signal processing, such as digital filters and quantizers, are written in the program memory 103 in advance.

The state variable memory 105 is the program memory]0
Stores state variables used when executing each program module stored in 3.

The address of the state variable memory 105 is specified by adding the value specified by the state variable pointer 106 and the relative address specified by the program memory 103.

The channel variable memory 107 is a memory for exchanging data between program modules when the program modules stored in the program memory 103 are executed. Addressing of the channel variable memory 107 is performed by adding the value selected by the selection circuit 108 and the relative address specified by the program memory 103. Address 0 of the channel variable memory 107 is an input register connected to the input port 112, and address 1* is an output register connected to the output port 113. Also,
Since the selection circuit 108 can also select the output of the state variable pointer 106, the state variable pointer 106 can also be used as a pointer for addressing the channel variable memory.

Next, a configuration for realizing the differential encoder shown in FIG. 2 will be described as an application example of the signal processor shown above.

The differential encoder shown in FIG. 2 has an input terminal 21 and a subtractor 22.
, a prediction filter 23 , a quantizer 24 , an inverse quantizer 25 , an adder 26 , and an output end 27 .

A subtracter 22 calculates a difference signal C between a signal It is sent to the output end 27. Further, this f-signal signal i is input to the inverse quantizer 25 to obtain a quantized residual signal qe.

An adder 26 calculates a sum signal r of the quantized residual signal qe and the output signal px of the prediction filter 23.

This sum signal r is input to a prediction filter 23 made up of a digital filter and used for calculation of a prediction filter for the next sample. By repeating the above operations, the bit rate of the signal X input to the input terminal 21 can be lowered and outputted from the output terminal 27. For more information, see Giant and others! 1984 Prentice H
Book 1 Digital Coding of Waveforms (DIGITAL C0L) ING published by a11
OF WAVEFOR, M8).

FIG. 3 shows the arrangement of program modules in the program memory 103 of FIG. 1 when realizing the digital signal processing of FIG. 2. An output program module 103-2 is stored at address 100, an addition module 103-3 that performs addition processing is stored from address 500, and output program module 103-2 is stored at address 500.
Subtraction module 103-4 that performs subtraction processing from address 0
is stored, a quantization program 2 module 103-5 that performs a quantization operation is stored from address 800, an inverse quantization program module 103-6 that performs an inverse quantization operation is stored from address 900, and a prediction program is stored from address 1000. Prediction filter program module 1 that performs filter calculations
03-7 is stored.

FIG. 4 shows the arrangement of the state variable memory 105 when realizing the above digital signal processing. A prediction filter area 105-1 for the prediction filter program module is allocated starting from address 50.

FIG. 5 shows the arrangement in the channel variable memo I) 107 when realizing the above digital signal processing. Address 0 is used as input register 107 Is and address 1 is used as output register 107-2. Address 10 is used as an input variable memo 1J107-3 to store the input signal Address 17107-5 is used as a memo 17107-5, address 13 is used as a quantizer output memo 9107-6 that stores the quantized signal i, and address 14 is an inverse quantizer output memo 1J107- that stores the element scolding difference signal qe. 7
Address 15 is used as an addition output memory for storing the sum signal r.

Below, seven steps of processing for realizing the differential encoding shown in FIG. 2 using the general-purpose digital signal processing apparatus of the present invention will be sequentially described.

(1) First step: When the block program counter 102 points to address 0, the first buttress 100 of the input program module 103-1 stored in the operation field at address 0 of the block command memory 101 points to the program counter 104. Address 0 of the input register 107-1 stored in the input channel field is transferred to the input channel pointer 109, and address 10 of the input variable memory 107-3 stored in the output channel field is transferred to the output channel pointer 109. It is transferred to the channel pointer 110.

Input program module 103- activated as a result
1, the selection circuit 108 first selects the output of the input channel pointer 109, specifies the address of the channel variable memory, and selects the input register 107 at address 0.
The input signal X stored as =1 is transferred to the arithmetic processing section 111. Next, the selection circuit 108 selects the output of the output channel pointer 110 to specify the address of the channel variable memory 107, and the arithmetic processing unit 11
The input signal X stored in 107-1 is input to input variable memory 107-1.
Store in.

(2) Second step: When the value of the block program counter 102 is incremented by 1 and points to address 1, the block command memory 102
The start address 600 of the subtraction module 103-4 stored in the operation input field at address 101 is transferred to the program counter 104, and the input variable memo! stored in the state variable field is transferred. Address 10 of prediction filter output memory 107-4 stored in the input channel field is transferred to the input channel pointer 109 and stored in the output channel field. The address 12 of the subtraction output memory 107-5 is transferred to the output channel pointer 110. The subtraction module 103- activated as a result
4, the selection circuit 108 first selects the output of the state variable pointer 106 and stores it in the channel variable memory 10.
Specify address 7 and enter input variable memo I at address 10.
The input signal X stored in Jl 07-3 is transferred to the arithmetic processing unit 111. Next, the selection circuit 108 selects the output of the input channel input channel 109 and specifies the address of the channel variable memo IJ 107.
The prediction signal X stored in the prediction filter output memory 107-4 at address 1 is transferred to the arithmetic processing unit 111. Next, the predicted signal px is subtracted from the input signal X in the arithmetic processing section.

Next, the selection circuit 108 selects the output of the output channel pointer 110 and selects the channel variable memo! 71
07 is specified, and the difference signal e, which is the result of the subtraction in the arithmetic processing section, is stored in the subtraction output memory 107-5.

(3) Third step: When the value of the block program counter 102 is incremented by 1 and points to address 2, the block command memory 102
The start address 800 of the quantization program module 103-5 stored in the operation field at address 1 and 2 is transferred to the program counter 104,
Address 12 of the subtraction output memory 107-5 stored in the input channel field is transferred to the input channel pointer 109, and address 13 of the quantizer output memo +7107-6 stored in the output channel field is transferred to the output channel. It is transferred to pointer 110. The quantization program module 103-5 activated as a result first selects the output of the input channel pointer 109 in the selection circuit 108, specifies the address of the channel variable memory 107, and then selects the output of the input channel pointer 109 in the selection circuit 108, and specifies the address of the channel variable memory 107. The difference signal e stored in is transferred to the arithmetic processing section 111. Next, the arithmetic processing section 111
quantization operation is performed to obtain a quantized signal i. Next, the selection circuit 108 selects the output of the output channel pointer 110 to specify the address of the channel variable memory 107, and the quantized signal i obtained by the arithmetic processing section 111 is stored in the quantizer output memory 107-6. Store.

(4) Fourth step: When the value of the block program counter 102 is incremented by 1 and points to address 3, the block command memory 102 is incremented by 1 and points to address 3.
The start address 900 of the dequantization program module 103-6 stored in the operation field at address 103 is transferred to the program counter 104, and the start address 900 of the quantizer output memory 107-6 stored in the input channel field is transferred to the address 13 of the quantizer output memory 107-6 stored in the input channel field. is transferred to the input channel pointer 109 and stored in the output channel field in the dequantizer output memory 107-7.
address 14 is transferred to the output channel pointer 110. The inverse quantization program module 103-6 activated as a result first selects the output of the input channel pointer 109 in the selection circuit IO8, specifies the address of the channel variable memory 107, and
The quantized signal i stored in the 3rd address quantizer output memo IJ107-6 is transferred to the arithmetic processing section 111. Next, the arithmetic processing section 111 performs an inverse quantization operation to obtain a quantized residual signal qe. Next, the selection circuit 108 selects the output of the output channel pointer 110 and specifies the address of the channel variable memory 107, and the quantized residual signal qe obtained by the arithmetic processing section 111 is sent to the inverse quantizer output memory 107. -7.

(5) Fifth step: When the value of the block program counter 102 is incremented by 1 and points to address 4, the block command memory 102
The start address 500 of the addition module 103-3 stored in the operation field at address 4 of 1 is transferred to the program counter 1-04, and the predictive filter output memo IJ1 stored in the state variable field is transferred to the program counter 1-04.
Adrus 11 of 07-4 uses the state variable pointer 106
The inverse quantizer output memo is transferred to and stored in the input channel field! Address 14 of J107-7 is transferred to the input channel pointer 109 and added output memo IJ stored in the output channel field.
Address 15 of 107-8 is transferred to the output channel pointer 110. The addition module 103-3 activated as a result first selects the output of the state variable pointer 106 in the selection circuit 108, specifies the address of the channel variable memory 107, and selects the output of the state variable pointer 106 at address 111, prediction filter output memo! The prediction signal 2 stored in 7107-4 is transferred to the arithmetic processing unit 111. Next, the selection circuit 108 selects the output of the input channel pointer 109 and specifies the address of the channel variable memory lO7, and addresses 144 inverse quantization output memo 1J107-7.
The quantized residual signal qe stored in is transferred to the arithmetic processing section 111. Next, the arithmetic processing unit adds the predicted signal px and the quantized residual signal qe.

Next, the selection circuit 108 selects the output of the output channel pointer 110 and selects the output of the channel variable memo I71.
07 is specified, and the addition result in the arithmetic processing section is stored in the addition output memory 107-8.

(6) Sixth step: When the value of the block program counter 102 is incremented by 1 and points to address 5, the block command memo IJ
The starting address 1000 of the prediction filter program module 103-7 stored in the operation field at address 5 of 101 is the program counter 104.
The start address 50 of the prediction filter area 105-1 stored in the state variable field is transferred to the state variable pointer 106, and the start address 50 of the addition output memory 107-8 stored in the input channel field is transferred to the state variable pointer 106. is transferred to the input channel pointer 109, and address 11 of the predictive filter output memory 107-4 stored in the output channel field is transferred to the output channel pointer 110. Prediction filter program module 103- activated as a result of this
7 first selects the output of the input channel pointer 109 in the selection circuit 108, specifies the address of the channel variable memory 107, and sends the sum signal r stored in the addition-camera IJ 107-8 at address 155 to the arithmetic processing section. Transfer to 111. Next, the arithmetic processing unit 111 performs a digital filter operation using the prediction filter area 105-1 as a filter delay to obtain a prediction signal px.

At this time, the filter delay address is specified in the prediction filter area 105 stored in the state variable pointer 106.
-1 start address and the program memo! This is done by adding the relative address specified from J103. Next, the selection circuit 108 selects the output of the output channel pointer 110 to specify the address of the channel variable memory 107, and the prediction signal X obtained by the arithmetic processing unit 111 is stored in the prediction filter output memo +7107-4. .

(7) Seventh step: When the value of the block program counter 102 is incremented by 1 and points to address 6, the block command memory 102
The start address 200 of the output program module 103-2 stored in the operation field at address 6 of 1 is transferred to the program controller 104, and the start address 200 of the quantizer output memory 107-6 stored in the input channel field is transferred to the program controller 104. Address 13 is transferred to the input channel pointer 109 and address l of the output register 107-2 is stored in the output channel field.
is transferred to the output channel pointer 110. The output program module 103-2 started as a result
First, the selection circuit 108 selects the output of the input channel pointer 109 and stores the channel variable memo IJ.
107 and transfers the quantized signal i stored in the quantizer output memory 107-6 at address 133 to the arithmetic processing section 111. Next, the selection circuit 108
The output of the output channel pointer 110 is selected to specify the address of the channel variable memory 107, and the quantized signal i stored in the arithmetic processing section 111 is stored in the output register 107-2.

FIG. 6 shows the arrangement within the block command memory 101 for executing the above operations.

By repeating the program shown in FIG. 6 every sampling period, the differential encoding process shown in FIG. 2 can be easily realized.

As shown above, by combining a program module that executes a basic digital signal processing algorithm prepared in advance using memory for input/output and memory for storing circular state variables, it is efficient and easy to use. A digital signal processing device can be realized.

(Effects of the Invention) The present invention efficiently executes various signal processing algorithms without repeating the creation of microprograms that require many man-hours by combining signal processing program modules that have been prepared in advance and perform efficient calculations. This has the effect of allowing you to create programs that

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a block diagram of an example of a differential encoder, Figure 3 is a layout diagram of an example of the program memory in Figure 1, and Figure 4 is a block diagram of an example of a differential encoder. K1
FIG. 5 is a layout diagram of an example of the state variable memory in the state variable memory in FIG. 1, FIG. 6 is a layout diagram of an example of the block command memory in FIG. In Fig. 1, 101...Block command memo IJ, 102
...Block program counter, 1o3...
...Program memory, 1o4...Program counter, 105...State variable meso, 1
06... State variable pointer, 107 Old... Channel variable memory, 108... Selection circuit, 1
09...Input channel pointer, 11O...
...Output channel pointer, 111-...J...
Arithmetic processing unit, 112...Input port, 113.
・・・・°・Output board＼−0・Gogi ≧ Toma wo turtle 0: Gikoζ ＼
＼ ＼ ＼ ＼ ＼ ＼ ζ牟 2nd 3rd drawing 6

Claims (1)

[Scope of Claims] 1. A program memory that stores a plurality of signal processing program modules, a state variable memory that stores state variables used during operation of the signal processing program modules stored in the program memory, and a channel variable memory for storing the input variables and output variables of each of the program modules stored in the program memory, the start address of each of the program modules stored in the program memory, the start address of the state variable memory used by the program module, and the program; The block command memory includes a block command memory that stores a block command consisting of the start address of an input variable and the start address of the output variable for the channel variable memory used by the module, and an arithmetic processing unit, and the block command stored in the block command memory. The commands of each of the program modules stored in the corresponding program memory are sequentially called, and the state variables and input variables necessary for the called program module are stored in the state variable memory as instructed in the block command. Digital signal processing characterized in that signal processing is performed by repeating operations of reading data and data in the channel variable memory, sequentially processing the data, and outputting the processing result to the channel variable memory specified in the block command. Method. 2. An arithmetic processing unit that performs arithmetic processing, a state variable memory connected to the arithmetic processing unit, a state variable pointer that specifies the address of the state variable memory, and a state variable pointer that is connected to the arithmetic processing unit and capable of inputting and outputting to the outside. a channel variable memory, an input channel pointer and an output channel pointer that specify addresses in the channel variable memory, and a selection circuit that connects at least one of the input channel pointer and the output channel pointer to an address section of the channel variable memory. , a program memory storing a program for controlling the arithmetic processing unit, the state variable memory, the state variable pointer, the channel variable memory, the input channel pointer, the output channel pointer, and the selection circuit; a block command memory that supplies data to the program counter, the state variable pointer, the input channel pointer and the output channel pointer; and a block program counter that specifies the address of the block command memory. A digital signal processing device comprising: