JPS6282433A - Information processor - Google Patents

Abstract

PURPOSE:To process quickly in parallel affairs which can be processed simultaneously between instructions, by executing and processing plural preliminarily determined continuous instruction by a microprogram which processes collectively this instruction word string. CONSTITUTION:An instruction word comparing circuit 4 compares an instruction word string in an executing instruction word string register 1 with that in an instruction word string register 2. An inter-instruction relation detecting circuit 3 detects whether the succeeding instruction refers to the result of the preceding instruction or not. Outputs of the comparing circuit 4, the detecting circuit 3, and the register 1 are received; and if the instruction word to be executed in the register 1 coincides with the instruction string registered in a register group 2 and the succeeding instruction refers to the result of the preceding instruction, a control memory 6 is started. The control memory 6 inputs the operation result of the preceding instruction to an operating circuit 7 to control the circuit 7 which executes the succeeding instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for executing instructions in an information processing device, and particularly to a method for high-speed processing of a plurality of consecutive instructions.

[Conventional technology]

Conventionally, in this type of information processing apparatus, each instruction was processed by a logically independent microprogram routine, although each instruction may be shared by several micronograms.

In other words, the contents of microprogram processing were not changed by the combination of consecutive instructions.

[Problem that the invention seeks to solve]

In the above-mentioned conventional information processing device, after the execution of one quick rjf program of the preceding instruction is completed [7], the execution of the following instruction's micro-program (/(enters. That is, the operation of the preceding instruction When the result is referenced by a subsequent instruction, the microprogram of the subsequent instruction is referenced after the microprogram/processing of the preceding instruction is completed, that is, after the operation result of the preceding instruction is stored in a general-purpose register or memory. 4. Before processing, read the operation result from the general-purpose register or memory - No. Therefore,
There is a drawback that processing time is required because the preceding instruction writes its operation result to the general-purpose register or memory, and the subsequent instruction reads it. - The drawback is that even instructions that are completely unrelated to each other, the arithmetic circuit can operate independently for each instruction, and instructions that can be executed simultaneously must be executed sequentially.

An object of the present invention is to provide an information processing device that eliminates the above-mentioned drawbacks.

[Means for Solving the Problems] The information processing device of the present invention includes a control memory that stores an actual microprogram for each instruction word individually, and a microphone EE f.
The instruction word string corresponding to the processing content of D Durham or the attribute string 4 of the instruction Jti: the instruction word string register group to be stored and the instruction word string register group corresponding to each register in the instruction word string register group (
7, a control information register 11 that stores and holds control information for executing the instruction dfi string or the attribute string of the instruction word in the register; an instruction string comparison circuit for comparing the contents of the instruction string and the contents of the register group; means for detecting a relationship between each instruction in the instruction string; and a means for detecting the relationship between the instructions and the ffi control information in the control information register group. Output 1 of the instruction string comparison circuit [Response 1-: Start of the microprogram in the control memory of the instruction word or instruction string to be executed in response to response 1? and a control circuit that determines and executes the response.

〔Example〕

Next, the present invention will be explained with reference to the drawings (-).

FIG. 1 is a schematic block diagram of one embodiment of the present invention. Execution instruction string register 1 holds an instruction word or instruction string to be executed. When the command or command string is executed, the next command string to be executed is supplied. The instruction word string reformator group 2 stores and holds a plurality of instruction word strings each consisting of a plurality of consecutive instruction words. However, information in the instruction word that is unnecessary for the control circuit 5 to determine the start address of the control memory 6 is not stored in the instruction string register group 2.

The control information notebook group 10 stores and holds control information for executing the instruction string held in the instruction string register group 2 in correspondence with each register of the instruction string register group 2. Specifically, in this embodiment, the start address of the control memory 6 is held.

The instruction comparison circuit 4 compares a necessary part of the instruction string in the execution instruction string register 1 to be executed from now with each of the instruction strings in the instruction string register group 2. In this embodiment, the instruction amount relationship detection circuit 3 detects whether the subsequent instruction refers to the result of the preceding instruction, that is, whether the eyestnation of the preceding instruction matches the source of the subsequent instruction. do. The control circuit 5 includes an instruction string comparison circuit 4. In response to the output of the instruction amount relationship detection circuit 3 and the execution instruction string register I, the instruction word in the execution instruction string register J to be executed is registered in the instruction string register group 2. When a subsequent instruction refers to the result of a preceding instruction that matches one of the columns, the control memory 6 is activated at the start address registered in the corresponding control information record group. The control memory 6 activated at the start address passes the operation result of the preceding instruction to the input of the operation circuit 7 within the operation circuit 7 without going through the memory 8 or the r1 general-purpose register 9, and executes the subsequent instruction. Controls the arithmetic circuit 7. On the other hand, when the instruction string to be executed does not satisfy the above-mentioned conditions, the control memory 6 is activated at the start address of a microprogram that individually processes each instruction in the instruction word.

Further, nine embodiments of the present invention will be described in detail using a specific example shown in FIG. In the instruction word string register group 2, three instruction word operation code strings shown in FIG. 2 are registered. Now, two consecutive instructions AI') I) CI, G2 (Gl←(Gl)
+ CG2) ) STJB Gl, G3 (G
l←(Gl)-(G3)) is execution instruction string register 1
The following describes the case where the program is supplied and executed within the program. The above instruction sequence adds the contents of general-purpose registers G1 and G2 and adds the result to G
Store it in 1.

Furthermore, the contents of 03 are subtracted from the result and the result is stored in 01.

The OP code (operation code) string "'ADD-8UB" in the execution instruction string register 1 is compared with each of the OP code strings in the instruction string recorder group 2 by the instruction string comparison circuit 4, and in this case, the OP code string "'ADD-8UB" is registered. Since it matches the first op code type ADD-8UB″', this fact is reported to the control circuit 5.The instruction amount relationship detection circuit 3
By comparing the destination field of the ADD instruction in execution instruction string 1 and the two source fields of the SUB instruction, the subsequent SUB instruction is
It reports to the control circuit 5 that the operation result of the D instruction will be referenced. Upon receiving the report signal, the control circuit 5 stores the start address (address 1000 in this case) of the microprogram in the control memory 6 that collectively processes the instruction word strings ADD and -8UB in the control memory in the control information recorder group 10. , and start the control memory 6 at this address 1000.

The activated control memory 6 controls the arithmetic circuit 7 to execute the instruction strings j to ADD-8TJB at the timing shown in FIG. That is, first, in the first machine cycle, the contents of general-purpose registers Gl and G2 are stored in register R1.
, R2, and in the second machine cycle set the addition result in register R3. In the third machine cycle, the contents of register R3 are stored in general-purpose register G1 and also set in register R1. G
Read the contents of 3 into register R2. In the fourth machine cycle, the result of subtraction of R1 and R2 is set in register R3. In the fifth and final machine cycle, the final result is stored in general-purpose register G1.

For reference, the ADD command and SUB command are not used in the device of the present invention.
FIG. 4 shows a time chart when the instructions are executed individually. As is clear from a comparison between FIG. 3 and FIG. 4, the device of the present invention requires 9 more units because it simultaneously executes the storage of the result of the preceding instruction and the reading of the address lands of the subsequent instruction. Processing time is slightly shorter.

In the following, we have explained a sequence of arithmetic instructions between registers, but the same applies to a combination of a preceding load instruction and an arithmetic instruction that references the load data, or a preceding arithmetic instruction and an instruction that stores its result. be. Furthermore, in the above embodiment, when the instructions in the instruction string are unrelated to each other, those instructions are executed individually. By performing batch processing, the storage of the result of the preceding instruction and the reading of the operand of the subsequent instruction are executed simultaneously, thereby increasing the speed. In yet another more preferred embodiment.

The attributes that classify instructions into types such as arithmetic instructions between general-purpose registers, arithmetic instructions between memory and general-purpose registers, load instructions that store the contents of general-purpose registers in memory, and store instructions that store the contents of general-purpose registers in memory are classified into OP codes. Instead, it is stored and held in the instruction word string register group 2. At that time, the instruction string comparison circuit 4 includes the execution instruction string register 1.
An attribute decoding circuit is added to classify the op codes within the above types into the above types.

〔Effect of the invention〕

As explained above, the present invention executes a plurality of predetermined consecutive instructions using a microprogram that collectively processes this instruction string, thereby allowing simultaneous processing to be performed between each instruction. This enables high-speed instruction processing.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an information processing apparatus according to the present invention, FIG. 2 is a diagram showing details of FIG. 1, and FIG. 3 is a time chart of arithmetic operations in FIG. 2. FIG. 4 is a time chart of calculation operations for conventional loading. ■...Execution instruction string register, 2...Instruction string register group, 3...Instruction amount relationship detection circuit, 4...Instruction string comparison circuit, 5...Control circuit, 6... control memory, 7
...Arithmetic circuit, 8...Memory, 9...General purpose register, 10...Control information register group.

Claims (1)

[Claims] 1. A microprogram that executes each instruction word individually;
A control memory that stores a microprogram that executes a sequence of consecutive instruction words as one processing unit, and stores and stores a sequence of instruction words or a sequence of instruction word attributes corresponding to the processing content of the microprogram. a group of instruction string registers to be executed, and a group of control information registers that store and hold control information for executing the instruction string or attribute string of the instruction word in the register corresponding to each register in the instruction string register group. an instruction string comparison circuit that compares the instruction string to be executed or the attribute string of the instruction to be executed with the contents of the register group; and means for detecting the relationship between each instruction in the instruction string. and the relationship between the instructions, the control information in the control information register group, and the start address of the microprogram in the control memory of the instruction word or instruction string to be executed in response to the output of the instruction string comparison circuit. An information processing device comprising: a control circuit that determines and executes a control circuit;