JPS628251A - Input/output control system - Google Patents

Abstract

PURPOSE:To speed up a data transfer covering over a discontinuous main memory address by providing a page counter and a page buffer of first-in first-out system at an input/output controller which performs the data transfer between a central processing unit and a magnetic disk. CONSTITUTION:An address register 101 which generates the address of the data on a main memory to be transferred to a magnetic disk device is driven by an address counter 109 At the address counter, a page counter 201 which indicates a low-order address to be transferred and a page buffer 202 which holds a high-order address corresponding to plural pages by the first-in first-out system. When the page counter 201 reaches to a page boundary, with operating the first detector 203, a signal PSFT302 which shifts the page buffer 202 is generated. And as far as a following channel command is not existed and a prohibition circuit is not set, with setting the second detector 206, the next page address loading is commanded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output control method, and in particular, in DMA data transfer in a virtual storage system, even if main memory addresses are discontinuous in page units, ``This invention relates to an input/output control method that switches main memory addresses at high speed and executes DMA data transfer.

BACKGROUND OF THE INVENTION In general, microprogram controlled input/output control systems operate in response to commands output from a central processing unit. This command includes a write command and a read command. I10
When data is transferred between the device and the central processing unit, the central processing unit sends a command to the input/output control unit.

Based on this command, the input/output control device decodes this command, sends the necessary commands to the device, controls DMA data transfer, and transfers the data.

When the data transfer is completed, this is notified to the central processing unit K by pressing the interrupt button.

Next, such an operation will be explained with reference to the drawings. FIG. 3 is a system configuration diagram of a general data processing system to which the input/output control method is applied. In Figure 3, %l is the central processing unit, ko is the input/output control unit, J is the magnetic disk device, 10/ is the address register, 10 is the data register, ios is the bus control circuit, /all is the microprocessor, 10k is ROM, tot.

is RAM, /17 is device control circuit, tot
is the data buffer, 10de is the address counter, llO
indicate data counters, respectively.

Figure 3 is a conceptual diagram showing the comparison between virtual address space and real address space. FIG. 3 is a conceptual diagram of a general channel program for commands from the central processing unit to the input/output control unit (only the parts necessary for DMA transfer are shown). FIG. 6 shows an example of a conventional channel program. Figure 5 is a conceptual diagram of the format of a magnetic disk device.

The operation of conventional DMA transfer will be explained with reference to FIGS. 3, 3, 6, and 3. As shown in Figure DA, when a data transfer request to the virtual address space of Figure DA ω occurs, the central processing unit/
), the usable area of the real address space is checked and allocated. At this time, main memory addresses that are continuous in the virtual address space are allocated discontinuously in the real address space. However, in this discontinuous allocation, the boundaries of the discontinuity are allocated to be an integral multiple of the sectors shown in FIG. The central processing unit 1 creates a channel program as shown in FIG. 6 in accordance with this real address space allocation, and issues commands to the input/output control unit. When the input/output control device receives a command, it sends a command to the microprocessor I.
O'l decodes the command and generates the command entry CCE t shown in FIG.

Take out the CCE from the central processing unit/1D, instruct the magnetic disk drive J to operate, then take out the command entries CGK and 7 shown in FIG. Set to.

Address A/ is set in address counter 109.

Next, the microprocessor 10 is the device control circuit 10.
Rito bus control circuit/117. ? Activates DMA data transfer. The device control circuit 10 issues a data transfer request to the bus control circuit 103 for each data transfer request. The bus control circuit 103 issues a data request to the bus (central processing unit/) every time there is a data transfer request from the device control circuit 107. The bus control circuit tOS adds the address register lo de and subtracts the data counter /10 every time data is transferred to and from the central processing unit l via the bus. When data counter/10 becomes empty, data counter/10 notifies microprocessor IO'l accordingly. The microprocessor data counter/
10 j: #) When the receiver receives the notification that the space is empty, it takes out the command entry ccg 41 shown in FIG. 6 from the central processing unit l, sets the range R in the data counter /10, and sets the address counter /θ Address A is set in D, and DMA data transfer is performed in the same manner as described above until data counter /10 becomes empty. This operation is performed until there are no more command entries OCR (up to command entry caEt in FIG. 4).

Recent magnetic disk drives J have improved data transfer speeds,
/-, 7MB/S very high speed devices are coming onto the market. When controlling such a device, the data stored in the magnetic recording device J is generally formatted by being divided into sectors as shown in the figure, and the minimum access to data is performed in units of sectors. . In addition, the interval between sectors is becoming smaller in proportion to the improvement in the data transfer speed of magnetic disk devices J (for example, there are devices where the interval between sectors is more than 10 μs). Like a conventional input/output controller, the microphone processor 10411 is activated by the central processing unit I each time the data counter/II becomes empty.
If a commercially available microprocessor is used to set a new data count and main memory address, it will require tens of μ8 or more.

This means that it is not possible to set a new data count or main memory address between sectors, and it is necessary to access the next sector by 7 rotations (-about /A
ms or more). Therefore, it is unnecessary to spend an extra time of four rotations to perform DMA data transfer to the real address space shown in FIG.
This requires a very large amount of time, resulting in a decrease in the performance of DMA data transfer and a decrease in system performance.

Problems to be Solved by the Invention As mentioned above, in the conventional input/output control system,
b) Real address space K When performing DMA data transfer, the time equivalent to 7 revolutions of the magnetic disk device 3 is spent at the time the main memory address changes, so a very large amount of time is required, and the DMA data transfer is delayed. The disadvantage was that the performance decreased, resulting in a decrease in system performance.

The present invention eliminates the above-mentioned disadvantages inherent in the conventional technology, and eliminates the time required for one revolution of the magnetic disk device 3 at the time of changing the main memory address even when performing data transfer, thereby eliminating the performance deterioration of DMA data transfer. The purpose of this invention is to provide a new input/output control method configured to improve system performance.

Means for Solving the Problems In order to achieve the above object, the input/output control method according to the present invention uses a channel program that includes discontinuous main memory addresses for DMA data transfer that differ in page units on the main memory. The input/output control device includes a page counter for DMA data transfer, a first-in-first-out control type page buffer, a first detection circuit for detecting the output of the page counter, and the first detection circuit. The second detection circuit is configured to include a second detection circuit for holding the output of the second detection circuit, and a prohibition circuit capable of prohibiting the operation of the second detection circuit.

Embodiment Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block configuration diagram of address control showing one embodiment for realizing the input/output control method according to the present invention.

That is, one embodiment of the present invention shown in FIG. 1 is an improved example of the address counter 1oip and the address counter 10 of the general input/output control devices shown in FIG.
Each element other than 9 is the same as that in FIG. 3, and will be described below with reference to a diagram in which FIG. 3 and FIG. 1 are combined. In FIG. 1, reference number 10/ is an address register, 109 is an address counter, 0/ is a page counter, 0 is a page buffer of first-in, first-out control system, and 03 is the output of page counter 20/. a first detection circuit for detecting, 201
I is an OR gate, 203 is an AND gate, and 06 is the first
a second detection circuit holding the output of the detection circuit 03;
07 is an error detection circuit, -〇za is an AND gate, ko09
1 and 2 respectively indicate a prohibition circuit that prohibits the operation of the second detection circuit OA and the second detection circuit θ.

FIG. 2 is an explanatory diagram for explaining one embodiment of the input/output control method according to the present invention. FIG. 1 is a diagram showing an example of a channel program for explaining an embodiment of the input/output control method according to the present invention.

DMA data transfer using the input/output control method according to the present invention will be described below with reference to FIGS.

Initially, when a data request for the virtual address space shown in Figure 4(a) occurs, the central processing unit l checks the usable area of the real address space and allocates it as shown in Figure 4(b). At this time, main memory addresses that are continuous in the virtual address space are allocated discontinuously in the real address space. Create a channel program as shown in the main memory and issue commands to the input/output controller.When the input/output controller receives the command, the microprocessor IO'l decodes the command. and the command entry CCE t, CC shown in Fig.
E is taken out from the central processing unit 1 and commands are given to the magnetic disk device 3 to operate. Next, the input/output control device
The command entry G (J3 shown in the figure)
, set the range -ΣR1 to R in the data counter/10, and set the lower/cobit (o
Hu) in the page counter 20/, and address A.
The upper bit (I; 37) of I is set in the page buffer 202 of the first-in, first-out control system. The input/output control unit then takes out the command entry G (3K tz) from the central processing unit l, and stores the upper bits (/, 7/) of the address A in the page buffer 20 of the first-in, first-out control system.
Seratos on 2.

The same operation is performed using the first-in-first-out control system page buffer, when w2 becomes Full, or when the data chain DC of command entry CCE = o, command chain y CO-
Repeat until O (last ccg) is detected. Page buffer 202 with first-in, first-out control method. Depth〉Channel program command entry CCE (number of addresses), then microprocessor 1olI is a prohibited circuit, 2oq
is set to prohibit the operation of the second detection circuit 206 and the error detection circuit λO. If the depth of the page buffer θλ of the first-in-first-out control method is the command entry OCR (number of addresses) of the channel program, then the prohibition circuit θ9
is not set.

The microprocessor 10 sets an address in the first-in, first-out control type page buffer, and then activates the device control circuit 10 and the bus control circuit lθ3 to start DMA data transfer. The device control circuit lθ7 issues a data request to the bus control circuit /θ3 for each data transfer request. The bus control circuit 103 issues a data request to the bus (central processing unit f/) every time there is a data transfer request from the device control circuit 10.

The bus control circuit 103 clocks a count clock C0LK every time data is sent/received to/from the central processing unit via the bus.
Generates the sot signal and starts the count clock C0LK30/
The page counter 20/ is incremented by the signal.

The output of the page counter Q and the output of the page buffer 20- are connected to an address register lθ/, and the output of the address register 10/ specifies a main memory address for each data transfer. Also, the data counter /10 is decremented every time data is transferred. The output debit (3:/l) of the page counter 20/ is connected to the first detection circuit 203. The page counter λO/ is added every time data is transferred, and when it reaches a certain value (in one embodiment, FFt), the detection circuit 03 operates and generates the PSFT 30 signal. The PSFT30 signal shifts the first-in, first-out page buffer. Furthermore, if the prohibition circuit 9 is not set, the PSFT30 signal sets the second detection circuit 06 and outputs the PBRICQ JO signal. It notifies you that the page buffer Ako0 of the first-out control method has become empty by one stage, and prompts you to set the remaining main memory address.Microprocessor ioq
When it detects the PBREQ 5oII signal, it takes out the command entry CCE from the central processing unit 1 and sets the main memory address to page buffer 0 in the first-in, first-out control system. The command entry OO taken out at this time
E is the last COE (DC-o, when 00-=go)
If so, set the % prohibition circuit -O9. The prohibited circuit code is not set unless it is the last COE.

Thereafter, similar operations are performed until the last GOTL. DMA data transfer is performed until the first-in, first-out control type page buffer 0- is empty and the data counter 110 is empty. The main points of the above explanation can be understood in more detail by referring to the time chart of FIG.

As explained above, the 1 microprocessor f1014 uses the first-in, first-out control method until the page count tacho O7 changes from 000 to FFt (from when the PSFT Jo signal is generated until the next generation). All you have to do is set the main memory address in the page buffer.

The data transfer rate of magnetic disk device J is s MB/
Even with S, it takes approximately m8 for the page counter 20/ to change from OOO to FFtrK. This means that even if the input/output control device is configured using a low-performance, inexpensive commercially available microprocessor, the main memory address can be switched within the sector interval time shown in FIG.

In the error detection circuit 0g, for some reason, the microprocessor could not set the main memory address in the page buffer A0 before the page counter O1 changed from 000 to FF. This is a circuit to detect this.

Effects of the Invention According to the present invention, as explained above, a channel program including discontinuous main memory addresses for DMA data transfer that differs in page units is provided on the main memory, and the input/output control device stores DMA data. A page counter for transfer, a page buffer using a first-in, first-out control method, a first detection circuit for detecting the output of the page counter, a second detection circuit for holding the output of the first detection circuit, and a second detection circuit. In addition to providing a prohibition circuit that can prohibit the operation of the circuit, it also eliminates the performance degradation of DMA data transfer using discontinuous main memory addresses that are different for each page in a virtual memory system, and as a result, the system The effect is that an input/output control method configured to improve performance can be easily provided.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of address control showing an embodiment of the input/output method according to the present invention, and FIG. 2 is a time chart for explaining an embodiment of the present invention.
FIG. 3 is a block diagram of the input/output control value device according to the prior art and the present invention, FIG. 4 is a conceptual diagram of virtual address space and real address space, and FIG. 5 is a conceptual diagram of a channel program.
Fig. 6 is a conceptual diagram of a channel program of a conventional input/output control device, K'y diagram is a conceptual diagram of a channel program of an input/output control method according to the present invention, and Fig. g is a conceptual diagram of a recording format of a magnetic disk device. FIG. l...Central processing unit%ko...I/O control device, 3.
...Magnetic disk device, 10/...Address register, 10λ...Data register, 103...Bus control circuit, 1oia...Microblosset t%
lO5...ROM, lob...RAM. 107...Device control circuit, 101...Data buffer, 109...Address counter, /10.
...Data counter, ko0/...Page counter%-
〇, 2...Page buffer of first-in first-out control method, 0
3...First detection circuit, ko0ri...OR gate, koor, kot...-AND gate, koQ6...
Second detection circuit, λ07...Error detection circuit, 209
...Prohibited circuit

Claims (1)

[Claims] It has a central processing unit, and an input/output control unit for controlling read/write operations of a magnetic disk device according to commands from the central processing unit, and the central processing unit and the magnetic disk unit are connected to each other via the input/output control unit. The input/output control method is configured to transfer data with a disk device, wherein the main storage of the central processing unit is provided with a channel program for the input/output control device, and the channel program includes a channel program for the input/output control device. Each page in the virtual system includes different and discontinuous main memory addresses, and the input/output control device is a DM.
A page counter for data transfer, a first-in-first-out control type page buffer, a first detection circuit for detecting the output of the page counter, and a second detection circuit for holding the output of the first detection circuit. The present invention includes a detection circuit and an inhibition circuit capable of inhibiting the operation of the second detection circuit, and is capable of performing DMA data transfer using discontinuous main memory addresses that differ in page units in a virtual memory system. An input/output control method characterized by realizing high-speed DMA data transfer by switching main memory addresses at high speed.