JPS628254A - Signal receiving and distributing circuit - Google Patents

Abstract

PURPOSE:To use all data lines for a data transmission by collating a part of an address received from a processor to the address of a self-device, receiving the remains as an order and controlling a subordinate device to be controlled. CONSTITUTION:A signal receiving and distributing circuit 3 receiving a signal through a bus 2 from a processor 1 collates column a1 of a part of an address from the address line 21 as the address of a self-device in a collation part 34. A remaining column a2 of the address line is received by an order register as an order to a subordinate device 4 to be controlled and fed to the device 4 to be controlled. After the data from an data line 22 is received by all data registers 33, it is fed to the device 4 to be controlled as the data.

Description

[Detailed Description of the Invention] [Summary] By transmitting the device address and order from the processor to the signal reception distribution circuit via the address line, all data lines can be used for data transmission. .

[Industrial application field]

The present invention relates to a signal reception and distribution circuit that can effectively utilize data transmitted from a processor.

The signal receiving and distributing circuit is selected by the address transmitted from the processor via the processor bus, and controls each controlled device under its control according to the order and data transmitted at the same time.

In such a case, it is desirable to be able to transmit data of as many digits as possible from the processor to the signal reception and distribution circuit.

[Prior Art] Fig. 3 is a diagram showing an example of a conventional signal reception distribution circuit.

In FIG. 3, a processor 1 is connected to a signal reception and distribution circuit 3 via a processor bus 2. In FIG.

In order for the processor 1 to cause the signal reception distribution circuit 3 to control the controlled device 4 under control, the processor 1 uses the device address given to the signal reception distribution circuit 3 as address a and transfers it to the processor bus 2.
An order specifying the control type of the controlled device 4 is sent to the address line 21 in the processor bus 2 as an order part d1, and data d containing data necessary for control as a data part d2 is sent to the data line 22 in the processor bus 2. Send to.

In the signal reception distribution circuit 3, the decoder 31 receives the address a transmitted via the address line 21, and outputs an activation signal e when it determines that it is the device address assigned to its own device, and sends the order It is transmitted to register 32 and data register 33.

The order register 32 and the data register 33 that have received the activation signal e store the order part d1 and the data part d2 transmitted via the data line 22, respectively, and use them for controlling the controlled device 4.

[Problem that the invention seeks to solve]

As is clear from the above description, in a conventional signal reception distribution circuit, the order section d1 and the data section d2 are received via the data line 22. The number of data lines 22 is
Since it is determined in advance, if the number of lines for transmitting the order part d1 is secured, the number of lines for transmitting the data part d2 will be compressed, and there is a possibility that sufficient data part d2 cannot be transmitted. . As a means to ensure the number of lines for transmitting the data part d2, the data line 22 is used twice, and the order part d1 is
It is also considered to transmit the data part d2 and the data part d2 independently as data d, but this would complicate the information processing process.
Furthermore, since the information transmission time increases, the processing capacity of the processor 1 is reduced.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, a collation means 310 compares some digits of an address a of a predetermined number of digits received from the processor 1 with the device address assigned to the own device as an address part a1.
The signal receiving distribution circuit 3 is provided with a receiving means 320 for receiving the other digits of the address a as an order part a2.

[Effect]

In general, address lines often have a sufficient number of lines to transmit an order part in addition to a sufficient number of lines to transmit a device address.

The present invention focuses on this point and transmits the order part together with the address part via the address line. As a result, all data lines can be used for data transmission, and data with a large number of digits can be transmitted.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a signal reception distribution circuit according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, a collating section 34 is provided as the collating means 310, and an order register 32 is provided as the receiving means 320.

In order for the processor 1 to cause the signal reception distribution circuit 3 to control the controlled device 4 under control, the device address assigned to the signal reception distribution circuit 3 is set in the processor bus 2 as address field a1, and the control target device 4 is controlled by the processor bus 2. An address a containing an order specifying the type as an order part a2 is sent to the address line 21 in the processor bus 2, and data necessary for controlling the controlled device 4 is sent to the data line 21 in the processor bus 2 as data d. Send on 22nd.

In the signal reception distribution circuit 3, the collation unit 34 receives the address part a1 transmitted via the address line 21,
It is compared with the device address assigned to the own device, and if the two match, an activation signal e is output and the order register 3
2 and the data register 33.

The order register 32 that has received the activation signal e stores the order part a2 transmitted via the address line 21,
The data register 33 also stores data d transmitted via the data line 22 and uses it to control the controlled device 4 .

As is clear from the above description, according to this embodiment, all the data lines 22 are used to transmit data d, so data d of a large number of digits can be transmitted.

〔Effect of the invention〕

As described above, according to the present invention, all data lines can be used for data transmission, and data of a large number of digits can be transmitted.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a signal reception distribution circuit according to an embodiment of the invention, and FIG. 3 is a diagram showing an example of a conventional signal reception distribution circuit. In the figure, 1 is a processor, 2 is a processor bus, and 3 is a processor bus.
is a signal reception distribution circuit, 4 is a controlled device, 21 is an address line, 22 is a data line, 31 is a decoder, 32 is an order register, 33 is a data register, 34 is a collation unit, 310
320 is a collation means, 320 is a receiving means, a is an address, al is an address part, a2 and dl are an order part, d is data,
d2 indicates a data portion, and e indicates an activation signal. Thighs are also pierced 1 mouth

Claims (1)

[Claims] Address (a) of a predetermined number of digits received from processor (1)
) collation means (310) for collating some digits of ) as an address part (a1) with a device address given to the device itself;
A signal receiving and distributing circuit comprising: receiving means (320) for receiving other digits of the address (a) as an order part (a2).