JPS628395A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To increase the action speed at the time of writing by separating a switch FET for writing and reading and enlarging the switch FET used at the time of writing. CONSTITUTION:For the gate width of respective FET, the maximum electric current value which flows to FET 100 and 101 is larger than the maximum electric current value which flows to FET 122 and 123, and further, the maximum electric current value which flows to FET 120 and 121 is larger than it. At the time of the writing action, one side of data lines 170 and 171 for writing is forcibly kept at the low electric potential, other side of them is forcibly kept at the high electric potential from the external part respectively and at the time of reading, only load elements 130 and 131 are connected to the data lines 170 and 171 for writing. At the circuit, since the switches FET 120 and 121 are larger, the high speed writing action can be expected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory cell for a static semiconductor memory device, and is particularly suitable for a GaAs LSI, etc., which require high speed rather than integration. related to memory cells.

[Background of the invention]

Conventional memory cells for GaAs memory LSIs were developed, for example, at the GaAs IC Symposium in 1983.
6X4 Bit Galarsenic Static Ram (A 256
As announced under the title ``X4 BIT GaAs 5TATICRAM) J'', it has a configuration as shown in Figure 2. In FIG. 2, 200 and 201 are FETs for memory retention, 210 and 211 are load FETs for supplying memory retention current, and 220 and 221 are FETs for connecting to data lines 270 and 271 when writing and reading information. It is a switch FET, and 1
It consists of memory cells for bits. 230, 23
1 is a load FET for pulling up the data line, 27
0.degree. 271 is a data line for passing mutually complementary bit information, and 260 is a word line for passing a word selection signal. In addition, 250, 251, 252 are high potential side power supplies,
255 is a low potential side power supply. Note that capacitors 240 to 244 are parasitic capacitances that inevitably occur when this circuit is actually configured on an LSI.

In the circuit of FIG. 2, for example, if node 280 is at high potential and node 281 is at low potential, FET2
00 is a cutoff state, FET201 is a conduction state, and 28
A high potential of 0 and a low potential of 281 are maintained. When the word line 260 becomes high potential in this state, the switch FET 22
0 and 221 become conductive, and a high potential and a low potential are read to the data lines 270 and 271, respectively. Initially 280°2
If the level relationship of the potential held at the node 81 is reversed, the potential read out to the data line will also be reversed. If the level relationship of the potentials held at the nodes 280 and 281 is made to correspond to 1 bit of information, the information can be read out by the method described above. To write information,
This is done by setting the word line 260 to a high potential while one of the data lines 270 and 271 is forcibly maintained at a high potential and the other at a low potential from the outside.

For example, while only the word line 270 is kept at a low potential, the word line 26
When 0 is set to a high potential, the node 280 becomes a low potential, and the FET 201 becomes cut off regardless of its previous state. In addition, the node 281 becomes a high potential, and the FET 20
0 becomes conductive.

Even if the word line 260 is set to a low potential after this, 28o.

281 nodes maintain this state. If only the data line 271 is initially kept at a low potential, the opposite state can be held.As in 1 or more, one bit of information can be written into, held in, and read out from the memory cell in FIG. .

By the way, in order to speed up the write operation of this circuit, it is necessary to increase the size of the switch FETs 220 and 221 to increase the current that charges and discharges the parasitic capacitances 240 to 242. However, if the maximum current value that can flow through FETs 220 and 221 is made larger than the maximum current value that can flow through FETs 200 and 201, the load FET 230 (
or 231), switch FET 220 (or 22
1) through memory holding FET200 (or 2o1
) may reverse the memory contents. This fear can be eliminated if the maximum current that can flow through the load FETs 230 and 231 is designed to be small, but the parasitic container 24
The current for charging 3,244 becomes smaller and the read operation becomes slower. Therefore, in the @ path of FIG. 2, it is difficult to achieve both high-speed operation and stable memory retention operation.

The circuit shown in Figure 3 was presented at the GaAs IC Symposium in 1983 as an ``Ultra-Low Power, High-Speed Gali Arsenic 256-bit Statistic Column'' (ULTRA-L).
OV POWER,)IIG)I 5PEED GaA
This is another conventional example published under the title s256-BI5TATICRAM) J. In Figure 3, 300,
301 is a FET for memory retention, 304 and 305 are diodes for level shifting, 306 and 307 are diodes for coupling capacitance, 308 and 309 are resistors for supplying current for level shifting, and 310 and 311 are for memory retention. Load resistance for supplying current, 320° 321 is a diode necessary for writing information, 303 is a third FET that is turned on and off depending on the stored information, 323 is a diode necessary for reading information, and this is all that is needed. The part is 1
Configure memory cells for bits. 333 is a load FET 37o for pulling up the read data line.

Reference numeral 371 indicates data lines for writing that are complementary to each other, 373 indicates a data line for reading, and 360 indicates a word line that also serves as a low potential side power supply. In addition, 350 and 354 are high potential side power supplies, 3
56 is a power supply for level shifting, and capacitors 340 to 344 are parasitic capacitances.

The memory holding portion of the circuit of FIG. 3 is the same as the circuit of FIG. 2 except that a level shift circuit is provided and a normally-on type FET is used. A read operation from this circuit is performed by lowering the potential of the word line 360. For example, when the node 380 is at a high potential, the FET 303 is in a conductive state, so when the potential of the word line 360 is lowered, the potential of the data line 373 is also lowered via the diode 323.

When the node 380 is at a low potential, the FET 303 is in a cutoff state, so even if the potential of the word line 360 is lowered, the data line 373 remains at a high potential. Therefore, the information stored in this circuit can be read out to data line 373. Further, the write operation is performed by lowering the potential of the word line 360 while keeping one of the data lines 370 and 371 at a high potential. For example, if the potential of the data line 370 is set high and the potential of the word line 360 is lowered, the FET 301
becomes conductive, the potential of node 381 decreases, and FE
T300 enters the cut-off state.

By the way, during the write operation of this circuit, the storage node 38
The current that lowers the potential of 1 (or 380) is FET301
(or 300), so the parasitic capacitance 340~3
In order to increase the current for charging and discharging 44 to increase the speed, it is necessary to increase the size of FETs 300 and 301. However, if the FET 300°301 is made larger, the parasitic capacitance 34
2 to 344 becomes large, which hinders speeding up. Therefore, it is difficult to speed up the write operation in the circuit shown in FIG. 3 as well.

[Purpose of the invention]

An object of the present invention is to increase the operating speed of a memory cell of a static semiconductor memory device, particularly the operating speed during writing.

[Summary of the invention]

As explained with reference to FIG. 2, in order to speed up the write operation of the memory cell, it is possible to increase the size of the switch FET, but if the switch FET is made large, there is a risk that the stored contents may be rewritten during reading. The present invention separates the write and read switch FETs, thereby making it possible to increase the size of only the switch FET used for writing.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, 100 and 101 are FETs for memory retention,
110 and 111 are load elements for supplying a memory holding current; 120 and 121 are switch FETs for connecting the storage node to the write data lines 170 and 171 when the word selection signal becomes a high potential; 122 and 123 is a switch F for connecting the storage node to the read data lines 172 and 173 when the word selection signal becomes high potential.
ET, and these parts constitute a memory cell for one bit. 130 to 133 are load elements for pulling up data lines, 170 and 171 are data lines for writing, 172 and 173 are data lines for reading, and 16
0 is the word line. Further, 150 to 154 are high potential power supplies, 155 is a low potential power supply, and capacitors 140 to 146 are parasitic capacitances.

In the circuit of Figure 1, the gate width of each FET is
From the maximum current value that can flow through 122 and 123.

Increase the maximum current value that can flow through FETs 100 and 101,
Furthermore, the maximum current value that can flow through the FETs 120 and 121 is made larger than that. The basic operation of the circuit in Figure 1 is almost the same as the circuit in Figure 2, and during a write operation, one of the write data lines 170 and 171 is forced to a low potential and the other to a high potential from the outside. When reading, the write data line is kept at 170°1.
Only the load elements 130 and 131 are connected to 71. In this circuit, switch FET120.121
Since this is large, high-speed write operations can be expected. on the other hand,
At the time of reading, the current flowing into the memory holding part through the FETs 120 and 121 is caused by the high resistance load elements 130 and 1.
31, and the current flowing from FETs 122 and 123 into the memory holding portion is limited by FET 100°101.
Since the current value is smaller than the maximum current value that can flow in the current, it is possible to prevent the stored information from being inverted due to the read operation. In addition, in the circuit shown in Figure 2, if a read operation is performed immediately after writing, it takes time for the level of the data line to recover, so there is a strong possibility that the read time will become longer; however, in the circuit shown in Figure 1, the read operation Since the data lines for use and write are separated, even if a large amplitude signal remains on the write data line immediately after writing, this will not affect the read time.

Note that the load elements 130, 130 are such that the current that charges the parasitic capacitance 145 (or 146) at the time of reading is the same as that of the load element 1.
This is to pull up the write data 8170 and 171 in advance in order to prevent the memory contents from being reversed due to the current exceeding the maximum value that can flow through the load element 130 (or 111). ,13
It is necessary to ensure that the current supplied from FET 100 and 101 has a sufficiently high resistance value so as not to become larger than the maximum current value that can flow through FETs 100 and 101 and invert the information in the memory cells. In addition to the read current that flows through FETs 122 and 123 during readout and the current that flows from load elements 130 and 131, the size of FETs 100 and 101 is determined by the instantaneous current that flows when parasitic capacitances 145 and 146 are discharged. It is also necessary to take this into consideration to prevent the memory contents from being reversed. In addition, the load elements 132 and 133 have a parasitic capacitance of 1
43 and 144 to have a sufficiently low resistance value to charge them at high speed.

FIG. 4 is a circuit diagram showing an embodiment in which the circuit of FIG. 1 is further improved. FIG. 4 shows the circuit of FIG. 1 with third and fourth FETs 402, which are turned on and off depending on the memory contents.
403 is added to prevent the read current from flowing to the memory holding FETs 400 and 401. Therefore, FET400, 401, 402, 40
3°420.423-. There is no particular restriction on the size relationship between 422 and 423, and 400 and 401 can be reduced to 420°421.
is increased to speed up the write operation, and 402,
403, 422, and 423 can be made larger to speed up the read operation.

In addition, in FIG. 4, the layout can be efficiently achieved by using so-called dual-gate type FETs that have two gate electrodes between the source electrode and the drain electrode for FETs 402 and 422, FETs 403 and 423, or both. At the same time, it is also possible to further increase the read current and read out data at high speed. Furthermore, since the readout speed is not related to the maximum current value that can flow through the FETs 400 and 401, the maximum current that can flow through the FETs 400 and 401 is Even if the value becomes smaller, the read speed will not become slower.

Fig. 5 shows an example in which the circuit shown in Fig. 4 is taken as a countermeasure against alpha ray soft error.
5.

As a result, it has a soft error resistance effect and at the same time
A memory cell that operates at high speed can be realized.

The circuit in Figure 6 replaces the FETs 400 and 401 in the circuit in Figure 4 with FET600 and load element 604 and FET601, respectively.
This is an example in which the load element 605 is replaced with the load element 605. 6th
In the circuit shown in the figure, even if FET 600 (or 601) is hit by alpha rays and momentarily becomes conductive, capacitances 641 (or 640) and 642 are
) before discharging through FET600 (or 601
) is recovered, the soft error will no longer occur. In this case, instead of adding the load elements 604 and 605, other means may be used to limit the current that flows when the FETs 600 and 601 are turned on. Also, capacity 640
642, it goes without saying that if the parasitic capacitance alone is insufficient, it is necessary to proactively provide a capacitive element. Furthermore, if the effect of the circuit of FIG. 6 is added by adding capacitors to the storage nodes 580 and 581 of the circuit of FIG. 5, soft error countermeasures will be doubled.

Figure 7 shows FETs 502 and 504, 503 and 50 in Figure 5.
This is an example in which the area occupied by the memory cell is saved by making the memory cell 5 common. In the circuit of Fig. 7, FET702,7
The maximum current value that can flow through FET 03 is larger than the maximum current value that can flow through FETs 722 and 723 and FET 700° 701, and the maximum current value that can flow through FETs 720 and 721 is
If the current value is made larger than the maximum current value that can flow through ET700, 701, it is possible to realize a memory cell that can perform high-speed writing without inverting the stored contents during reading and has the soft error resistance effect of the previous application. can.

The circuit shown in FIG. 8 is an example in which a source follower is used in the read portion. In the source follower circuit, it is possible to drive a load with a low resistance value with a small FET, so when the parasitic capacitance attached to the read data lines 872 and 873 is large, the resistance values of the load elements 832 and 833 are made opposite to increase the speed. It is possible to achieve this. In addition, the 8th
In the circuit shown in the figure, FETs 802 and 822 or FETs 802 and 822,
Dual gate FETs can also be used for ETs 803 and 823, or both. Further, in the circuit shown in FIG. 8, it is also possible to take measures against soft errors as shown in FIG. 5 or 6.

9 and 10 are circuit diagrams showing other embodiments of the present invention, respectively. The configurations of the memory cells in the circuits of FIGS. 9 and 10 are exactly the same as those of the circuits of FIGS. 1 and 4, respectively, but the states of the word lines and data lines are different. In other words, the word line is divided into two types, one for writing and one for reading, and when reading, the reading switch FET 922 is used.
Only ゜923 (or 1022.1023) is made conductive, and when writing, write switch FET920,
921 (or 1020, 1.021) or all switch FETs 920 to 923 (or 1020 to 102
3) is made conductive. Figure 9 or 1
It is clear that the circuit shown in FIG. 0 has the same effect as the circuit shown in FIG. 1 or 4, and that the measures against soft errors shown in FIGS. 5 to 7 can be applied.

FIG. 11° shows an embodiment in which the memory holding FET is made into a normally-on type by using a level shift circuit. Although the circuit of FIG. 11 is the circuit of FIG. 1 in which the memory holding FET is of a normally-on type, this replacement can be applied to all the embodiments described so far. Further, in all the embodiments described so far, it is possible to make the switch FET a normally-on type by designing the potential of the word line to an appropriate value.

Furthermore, in the circuit of FIG. 8, the memory holding FET 80
F with 0,801 set to normally off type, ET802
, 803 can also be of normally-on type. This makes it possible to further reduce the resistance values of the load elements 832 and 833, thereby increasing the speed.

In addition, in all the embodiments described above, two signals complementary to each other are read out from both storage nodes, but if the readout signal has a sufficient noise margin, it is also possible to read out only one signal. Effects] As described above, according to the present invention, it is possible to speed up the operation of a memory cell.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of a conventional circuit, Fig. 3 is a circuit diagram showing another example of the conventional circuit, and Figs. FIG. 11 is a circuit diagram showing an embodiment of the present invention. 100.101,200,201,300,301゜4
00.401,500,501,600,601゜70
0.701,800,801,900,901°100
0, 1001.1100.1101...F for memory retention
ET, 303, 402,403. 502. 503
,602°603, 702. 703,802. 8
03,1002゜1003...Third or fourth FET that turns on and off depending on the memory contents, 504,505.
・FET for memory retention provided as a countermeasure against soft errors,
604,605...Load element provided for soft error countermeasure, 304゜305, 1104.1105...Level shift diode, 306.307...Diode for coupling capacitance, 1106゜1107...For coupling capacitance Element, 308, 309... Resistor for supplying current for level shift, 11011°1109... Load element for supplying current for level shift, 110, 11
1,410,411,510゜511.610,611
,710,711,810°811,910.911.
1010.1011.1110゜1111...Load element for supplying memory retention current, 210.211...
- Load FET for supplying memory retention current, 310,
311...Load resistance for supplying memory retention current,
120,121,420°421.520,521,6
20,621,720°721.820,821,92
0,921,1020°1021,1120.1121
...Writing switch FET, 122.123,
422,423,522,523.622,623,7
22,723,822°823,922.923.10
22.1023.1122°1123...Switch FET for reading, 220°221...Switch FET for placing and reading, 320,321...
Writing diode, 323...Reading diode, 130° 131.132, 133, 430,
431,432.433,530,531,532,5
33°630.631,632,633,730,73
1.732,733,830,831,832°833
,930.931.1030.1031.1130゜1
131, 1132.1133...Data line load element, 230°231.333...Data line load FET
, 140°140.142,143,144,145,
146°240.241,242,243,244,3
40°341.342,343,344,440,44
1°442.443,444,445,446...parasitic capacitance, 640,641,642...parasitic capacitance or capacitive element, 150,151,152,153°154.
250,251,252,350,354°450.4
51,452,453,454,550°551.55
2,553,554,650,651゜652.653
,654,750,751,752゜753.754,
850,851,852,853゜854.950,9
51,952,1050,1051゜1052, 115
0.1151.1152.1153.1154...High potential side power supply, 155,255,455,555,655
゜755.855,85.6,857,955,105
5゜1155...Low potential side power supply, 356.1156.
...Power supply for level shift, 160, 260, 460,
560゜660.760, 860.1160--Word line for reading and writing, 360... Word line that also serves as a low potential side power supply, 960, 1060... Word line for writing, 961.1061...・Word line for reading, 170.171, 370, 371, 470
,471°570.571,670,671,7,70
,771°870,871.1170.1171...
Data lines for writing, 172, 173, 373, 47
2,473°57.2,573,672,673,77
2,773°872, 873.1172.1173...
・Data line for reading, 270, 271, 970, 9
71.1070゜χ 1 Zuhai 2 Zuton 4 Figure 7th ￥ 3 Figure

Claims (1)

[Claims] 1. A device comprising a pair of memory FETs whose drain electrodes and gate electrodes are cross-connected to each other, and a pair of loads for supplying current to the pair of memory FETs. In a memory circuit comprising a memory holding portion and a pair of switch FETs connected between mutually complementary data lines and the memory holding portion and turned on and off by a word selection signal, the pair of switch FETs shall be used exclusively for writing information, and in addition to this, there is a switch FET used for reading.
At least one switch FET is provided, and this separately provided switch FET
1. A semiconductor memory circuit, characterized in that the circuit is connected between a data line and a memory holding portion and is turned on and off by a word selection signal. 2. The mutually complementary data lines mentioned above shall be used for writing information, and in addition to this, at least one data line used for reading shall be provided, and this separately provided data line shall be connected to the separately provided switch used for reading. 2. The semiconductor memory circuit according to claim 1, wherein the semiconductor memory circuit is connected to a FET. 3. Two types of word selection signals are used, one of which turns on and off the above-mentioned pair of write-only switch FETs, and the other turns on and off the above-mentioned separately provided switch FET used for reading.
The semiconductor memory circuit according to claim 1 or 2, characterized in that the ET is turned on and off. 4. At least one FET that turns on and off depending on stored information is provided separately from the pair of memory holding FETs, and the separately provided switch FET is connected to the memory holding part via this FET. A semiconductor memory circuit according to claim 1, 2, or 3, characterized in that: 5. Separately provided F that is turned on and off according to the above stored information
5. The semiconductor memory circuit according to claim 4, wherein the ET and the separately provided switch FET constitute a dual gate type FET. 6. Separately provided F that is turned on and off according to the above stored information
6. The semiconductor memory circuit according to claim 4, wherein the ET operates as a source follower. 7. Claim 1, characterized in that the maximum current value that can flow through the pair of memory holding FETs is smaller than the maximum current value that can flow through the pair of switch FETs. The semiconductor memory circuit according to the second term, the third term, the fourth term, the fifth term, or the sixth term.