JPS628400A - Capacitor memory circuit - Google Patents

Abstract

PURPOSE:To enable using a capacitor with a large parasitic capacity as the capacitor for a memory without reducing the action speed by separating electrically other capacitor for the memory from a reading amplifier at the time of the writing and reading action of the signal. CONSTITUTION:Between respective capacitors 4-1-4-n for the memory and the negative polarity input terminal of a reading amplifier 2, the switch is added, only the capacitor for the memory during the reading action is connected to the negative polarity input terminal of the reading amplifier 2 and other capacitor for the memory is electrically separated. Thus, the parasitic capacity found at the negative polarity input terminal can be widely decreased and the action speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a capacitor memory circuit, that is, a memory circuit in which an analog signal is stored in a capacitor in the form of electric charge and read out.

[Background of the invention]

Now, as a delay line for analog signals that can be integrated into LSI,
There is a charge-coupled device (hereinafter abbreviated as COD),
1) Product yield is poor due to special manufacturing process (
2) There are problems such as difficulty in lowering the power supply voltage.

Switched capacitor technology (hereinafter referred to as 8C technology) is used as an analog signal delay line that can alleviate these problems.
A delay line using SC (hereinafter referred to as SC delay line) has been proposed.

A capacitor memory circuit constituting such an SC delay line is described in Japanese Patent Application Laid-Open No. 150193/1983. This memory circuit will be explained below using FIG. 2 as a conventional example. 〇 FIG. 2 is a circuit diagram showing a conventional example of a capacitor memory circuit ◇ In the same figure, 1 is a signal input terminal, 2- is a readout amplifier, 3 is an output terminal, (4-1) to (4-n) are storage capacitors, and (5-1) to (5-n) are write switches, each consisting of an NMO8 transistor.1. (6-1) to (6-n) are readout switches, each consisting of an NMO8) transistor, 7 is a short-circuit switch between the input and output of the readout amplifier 20, consisting of an NMO8) transistor, and 8 is a switch drive circuit. .

At the time of writing, the input/output shorting switch 7 and the writing switch (5-1) (when writing to the storage capacitor 4-1) are turned on. If the gain of the readout amplifier 2 is sufficiently large, the potential of the negative input terminal of the readout amplifier 2 is equal to the potential of the positive input terminal, that is, the ground potential, so if the input signal from the input terminal 1 is ein, then
The input signal ei is connected between both ends of the storage capacitor (4-1).
A voltage of n is applied. When the writing switch (5-1) and the input/output shorting switch 7 are turned off, there is no charge discharge path, so the input voltage e is applied to the storage capacitor (4-1).
in is retained.

At the time of reading, the read switch (6-1) is turned on (however, when reading the contents of the storage capacitor 4-1), the storage capacitor (4-1) is connected between the input and output of the read amplifier 20. Even in this state, there is no charge discharge path, so the voltage across the storage capacitor (4-1) is
The voltage ein remains and, as a result, the readout amplifier 2
A potential difference ein occurs between 0 input and output. If the gain of the readout amplifier 2 is sufficiently large, the potential of the negative input terminal is the ground potential, so the output voltage of the readout amplifier 2 is the voltage ef.
It becomes n.

As described above, in the capacitor memory circuit shown in FIG. 2, in which the analog input voltage is written to the storage capacitor, held, and read out, the number of storage capacitors is N, and the repetition frequency of writing and reading operations is 'C'.
If L, this memory circuit has a delay time (N/fcL)
Can be used as an analog signal delay line.

This memory circuit has a major feature in that it is almost unaffected by the offset voltage of the read amplifier 2 and by variations in the capacitance of the storage capacitor.

The write and read operation speed of this capacitor memory circuit depends on the parasitic capacitance 9 seen on the line of the negative input terminal of the read amplifier 2 and the parasitic capacitance f seen on the output line.
It is a function of f1lo, the storage capacitor (4-1) (when writing to or reading from the storage capacitor 4-1), and the mutual conductance of the read amplifier 2, and the larger the capacitance value, the slower the operating speed. .

In particular, the readout speed largely depends on the value of the parasitic capacitance ff19 seen on the line of the negative polarity input terminal ◇The contents of this parasitic capacitance fj19 are the input capacitance of the readout amplifier 20 and the NMO8 that constitutes the input/output shorting switch 7) This is the sum of the PN junction capacitance tJEf near the drain diffusion layer of the transistor and the capacitance I associated with the storage capacitors (4-1) to (4-n). Number of storage capacitors (i.e. number of memories)
is large, storage capacitors (4-1) to (4-n
) becomes dominant.

Therefore, when a storage capacitor with a large parasitic capacitance is used, the operating speed decreases.

[Purpose of the invention]

An object of the present invention is to provide a capacitor memory circuit in which even a capacitor with a large parasitic capacitance can be used as a storage capacitor without reducing the operating speed.

[Summary of the invention]

In order to achieve the above object, in the present invention, a switch is added between each of the storage capacitors (4-1) to (4-n) and the negative polarity input terminal of the readout amplifier 2 to Connect only the storage capacitor during read operation to the negative input terminal of read amplifier 2,
Other storage capacitors were electrically isolated.

As a result, the parasitic capacitance seen at the negative input terminal can be significantly reduced, and the operating speed can be improved.

[Embodiments of the invention] FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In this figure, elements or blocks having the same reference numerals as those in FIG. 2 have the same functions. (l l
1) to (11-n) are added write switches consisting of MOS transistors, (12-1)
. . . (12-n) are similarly added read switches which are composed of MOS transistors. The basic principle of 0 write and read operations is the same as that described above with reference to FIG.

At the time of writing, the write pulse φ is output from the switch drive circuit 8, the write MOS transistor switches (5-1) and (11-1> are turned on, and the set pulse φ8 is turned on.
MOS transistor switch 7 for shorting between input and output
turns on and writes the signal voltage t- from input terminal 1 to the storage capacitor (4-1).

During readout, the readout pulse φ8□ from the switch drive circuit 8 turns on the readout MO8) transistor switches (6-1) and (12-1), and the storage capacitor (4-1) turns on the readout amplifier 2. The holding voltage is read between the input and output.

Below, the parasitic capacitance seen at the negative input terminal of the readout amplifier 2 is expressed by the switches (11-1) to (11-n).
, (12-1) to (12-n) will be compared.

A case will be described in which a MOS capacitor is used as a storage capacitor. FIG. 3 shows a schematic cross-section of the vertical structure of a MOS capacitor, and FIG. 4 shows its equivalent circuit diagram.

In this example, the substrate is of N type.

In FIG. 3, 13 is an N-type semiconductor substrate, 14 is a P-type diffusion layer and an electrode on the semiconductor side of the MOS capacitor, 15 is an oxide film, and 16
is made of aluminium, polysilicon, or the like, and forms the metal side electrode of the MOS capacitor. 17*18 is a terminal.

This structure consists of an oxide film capacitance (19 in FIG. 4) between electrodes 16 and 14 and a junction capacitance (19 in FIG. 4) formed between electrode 14 and substrate 13.
20) in FIG. This junction capacitance 20 becomes a parasitic capacitance that appears at the negative input terminal of the read amplifier 2 in the memory circuit shown in FIG. The capacitance value of this junction capacitor 20 is about 60 times the capacitance value of the oxide film capacitor 19 which becomes a storage capacitor. In other words, if the capacitance value of the storage capacitor is set as o, spp, the parasitic capacitance is o, apF'
It also becomes.

First, in Figure @1, switches (11-1) to (11-
Consider the case where there are no p(12-1) to (12-n).

Regarding the capacitor (4-1), the electrode 16 of the MOS capacitor
The other capacitors (4-2) to (4-n) are connected in the same way. Then, the parasitic capacitance generated in the input terminal line becomes at least (0,5XN) pF. However, N is the number of storage capacitors.

Regarding the capacitor (4-1), the MO8 capacity electrode 16 side is the input terminal, and the electrode 14 side is the switch (5-1).
and (6-1), and if the same applies to other capacitors, the junction capacitance 20 (FIG. 4) will be (0,2XN) pF. Actually, MOS transistor switches (5-1) to (5-n') and (6
Since the junction capacitance h't of the drain diffusion layer -1) to (6-n) can also be seen, it becomes even larger.

Next, switch (11-1) to (1t n)y(12-
Consider the case where 1) to (12-rt) are provided.

Switches (11-1) to (11-n), (12-1) to
The junction capacitance of the drain diffusion layer of a (MOS) transistor of a size used for (12-n') transistor is 0.
Since it is 02 pF, the total amount is about (0,04XN) pF. Therefore, switches (11-1) to (11-n
), (12-1) to (12-n), it becomes possible to increase the operating speed by approximately 5 to 12 times.

! 1t! FIG. 5 shows another embodiment of the present invention. @1 Elements or switches with the same symbols as in the figure have the same functions.

The circuit in Figure 5 differs from that in Figure @1 in that the additional switches for writing (11-1) to (11-n) and the additional switches for reading (12-1) to (12-n) are also used. It is. When writing to the storage capacitor (4-1), the write pulse φ7 from the switch drive circuit 8 turns on the MOS transistor switch (5-1), and the write/read pulse φWRI turns on the dual-purpose switch (19-1). 1) is turned on, and the input/output shorting switch 7 is turned on by the set pulse φ3.

At the time of reading, readout pulse φ8□ causes readout M.
The OS) transistor switch (6-1') is turned on, and the MOS) transistor switch (6-1') is turned on by the deposition pulse φWR1.
9-1) is turned on. In the case of FIG. 5, the number of types of switch drive pulses increases, but since the parasitic capacitance due to the additional switch is halved, the operating speed is further doubled.

FIG. 6 shows still another embodiment of the present invention. ◇Elements or blocks having the same reference numerals as in FIG. 1 have the same functions.

In Figure 6, 20, 21, and 22 are constant voltage sources, respectively;
23.24 are each PMO8) transistor, 25.2
6 are NMOS) transistors, and these 20 to 2
The read amplifier 2 is composed of 6O elements.

The difference between the circuit shown in Figure 6 and that shown in Figure 1 is:
This concerns the configuration of the readout amplifier.

@Figure 7 shows the input/output DC characteristics of the readout amplifier shown in Figure 6. The basic principle of write and read operations is the first
This is the same as described with reference to the figures.

During writing, the voltage on the input/output terminal line of the read amplifier is at point A in the graph shown in FIG. If the voltage at the signal input terminal during writing is ein, the operating point of the read amplifier during reading is point B. The potential difference in the vertical axis direction between points A and B corresponds to the potential difference between both ends of the storage capacitor.

When using a readout amplifier having characteristics as shown in FIG. 7, the dynamic range of the input signal from the signal input terminal 1 is the output voltage range from point A to point 0 in FIG. #I7. In this case, the MOS transistor switch (5
-1) to (5-n) and (6-1) to (6-n) are MOS) transistor switches (11-1) to (11-n) (12-1) to (1
2n ) drain-source potential is much higher than that of ◇
If an NMOS) transistor is used as a switch, a MOS) transistor switch (11-
1) - (11-n), (12-1) - (12-n) size (gate width, ) is MOS) transistor switch (5
-1)~(5n)s(61)~(6-n) O1/
About 3 is enough.

This means that the effect of reducing the parasitic capacitance due to the addition of the switch exists even when the parasitic capacitance of the storage capacitors (4-1) to (4-n) is small. This point will be explained below.

The parasitic capacitance when there is no switch is the capacitor (4-1
) circuit is MOS) transistor switch (
5-1) e (6-1)o drain or source diffusion layer junction capacitance MCCx) and storage capacitor (4-
1) Capacity/amount (assumed to be C4) On the other hand, the switch (11-1
), (12-1) is the drain or source diffusion false O junction capacitance fjk (assumed to be C2) of the MOS transistor switches (11-1) and (12-1).

Practical values are: Ct = 0.12 oF, C9
-0.04DFC4-0.59F, so if there is no switch it will be 0.19F and if there is a switch it will be 0.04pF, which can be reduced to less than half. In this way, even if the storage capacitor has no parasitic capacitance, the operating speed can be improved.

As described above, by adding a switch, the operating speed can be improved regardless of the presence or absence of parasitic capacitance, so any capacitance that can be manufactured by the adopted process can be used as a storage capacitor. This means that the capacitor memory circuit can be manufactured using the simplest process, that is, a general-purpose process, which has the effect of reducing costs.

FIG. 8 shows a cross-sectional view of a vertical structure of a capacitor that can be manufactured using a CMOS process. However, in this example, the case where the substrate is N type is shown, but if the substrate is P type, the situation can be completely reversed.

In the wXs diagram (a), 27 is an N-type substrate, 28 is a thick field oxide film, 29 is an oxide film, 30 is polysilicon and forms the lower electrode of the capacitor, and 31 is a thin oxide film formed by reoxidation. , 32 constitute the upper electrode of the capacitor from aluminum or the like. With this capacitance, a high unit area capacitance value and a small parasitic capacitance can be achieved, but a process for forming the capacitor is required.

In (b), a 33uP type diffusion layer (well layer), 34
is an oxide film that utilizes the capacitance between polysilicon and the well.

In this example, it is preferable to set the P-type well layer side to a high potential.

Also, there is a large parasitic capacitance in the well side electrode.

(C) is a PMO 8) transistor, and 35 is a drain and source diffusion layer that utilizes the polysilicon gate and the capacitance between the drain and source. In this case, it is best to set the gate side to a low potential.

(d) is a depression type PMO8) transistor, and 36 is a P-type ion implantation layer.

(d) a. Although it is possible to set the polysilicon gate side to a high potential if the degree of depression is high, it is generally better to set it to a low potential side.

(e) is an NMO8) transistor, and 37 is a drain/source N-type diffusion layer. In this example, it is an 0(f)H depletion type NMO8) transistor in which the polysilicon gate side is preferably set to the high potential side, and 38 is an N-type layer. In this example as well, depending on the degree of depression, the polarity of the electrode does not matter, but it is desirable to use the polysiliman gate side as the high potential side.

For the reasons mentioned above, by adding a switch, 88
All capacitances shown can be used as storage capacitors. In particular, the use of depletion type MOS transistors shown in FIGS. 8(d) and 8(f) is very effective because a wide dynamic range can be obtained without complicating the process steps.

That's all #! Although the description has been made based on the conventional memory circuit shown in FIG. 2, the present invention is also applicable to other types of memory circuits.

#! FIG. 9 shows an example in which the present invention is applied to another type of memory circuit. Elements or blocks with the same symbols as in FIG. 781 have the same functions.

In FIG. 9, 39 is a read capacitor.

During writing, the switch (s-i) is activated by the write pulse φ7□ from the switch drive circuit 8.

(11-1) is turned on, input/output short-circuit switch 7 is turned on by set pulse φ8, and memory capacitor (4-1) is turned on.
The input voltage from input terminal 1 is written to .

During reading, the reading switch (6-1) e (12-1) is turned on by the reading pulse φ8□. When turned on, both ends of the capacitor (4-1) are connected to the ground potential, so the charge held in the capacitor moves to the read capacitor 39. If the capacitance values of the storage capacitor (4-1) and the readout capacitor 39 are equal, the potential difference between both ends of the readout capacitor will be equal to the holding voltage of the storage capacitor (4-1), so the input voltage will be applied to the output terminal 3. Read out.

Even in this memory circuit, the operating speed depends on the parasitic capacitance of the input terminal of the readout amplifier 2.
The operation speed can be improved by adding ~(11-r1), (12-1), and (12-n).

As described above, it is clear that the present invention can be applied to other types of capacitor memory circuits.

〔Effect of the invention〕

According to the present invention, even a capacitor with a large parasitic capacitance can be used as a storage capacitor in a capacitor memory circuit.

This allows MOs formed by general-purpose MOS processes to
Since 8 capacitors can be used as storage capacitors, costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a circuit configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a conventional capacitor memory circuit, FIG. 3 is a schematic cross-sectional view of a vertical structure of an MO8 capacitor, and FIG. The figure is a circuit INr diagram showing a circuit having the structure shown in FIG. 3, FIG. 5 is a circuit diagram showing another embodiment of the present invention, and FIG. 6 is a circuit diagram showing still another embodiment of the present invention. , Fig. 7 is a graph showing the input/output DC characteristics of the readout amplifier shown in Fig. 6, Fig. #8 is a schematic cross-section of the vertical structure of various capacitors, and Fig. 9 shows yet another embodiment of the present invention. Circuit diagram, 0 Symbol explanation 2... Readout amplifier, (4-1) to (4-n
)... Memory capacitor, (5-1) ~ (5-
n)...MO8) transistor for write switch, (6-1) to (6-n)...MO8) transistor for read switch, (11-1) to (11-n)
)... MO8) transistor for write switch, (12-1) to (12-n)... MO8) transistor for read switch, (19-1) to (19-
n)・・・・・・M for writing/reading switch
O8) Langista Agent Patent Attorney Akio Namiki Figure 1 Figure 2 Figure 3 P-type dispersion layer! Figure I4 Yabumasa Line Winter Quantity 5MJ Figure 6

Claims (1)

[Claims] 1) In a capacitor memory circuit in which one readout amplifier is commonly connected to multiple storage capacitors, during signal write and read operations, the capacitor that is the target of the operation is removed. A capacitor memory circuit comprising means for electrically disconnecting a storage capacitor from the readout amplifier.