JPS6284494A - Read only memory - Google Patents

Abstract

PURPOSE:To increase the number of data rewritable times by providing a timer circuit and selectively erasing data prior to data rewriting in accordance with write data. CONSTITUTION:When a boost circuit 1 boosts a voltage to an erasable and rewritable voltage VPP, the timer circuit 3 outputs the voltage VPP at a high potential and a write timing signal WT at a low potential in the first and later halves during one period. Write data D0-Di with a voltage fluctuation of VPP are impressed on the drains of selected memory cells M0-Mi from a data holding circuit 2. In the first half of the WT, the memory cell to be erased has a control gate at a VPP potential and a drain at a low potential, and then said cell is erased. In the memory cell to be written, its control gate and drain come to VPP potential, and therefore previous data is held. In the latter half, a low potential is impressed to the control gates of the memory cells M0-Mi, and the memory cell to be erased holds erasure data, while data is written in the memory cell to be written.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only memory, and particularly to a read-only memory in which data can be rewritten.

[Conventional technology]

In electrically erasable programmable read-only memory (hereinafter referred to as EEFROM), an automatic erase function has been put into practical use in which when data is rewritten, memory cells are automatically erased and then data is written. has been done.

Conventionally, this glazed read-only memory has been erased, that is, set to the data 1'' state, regardless of the pre-fixed data state, and then the write data l Q M
is written, so the pre-fixed data is 10
If the write data is 101 in -, "0" is erased and changed to Jl, and 10- is written again.

For EEPROMs, the number of times they can be rewritten is an important characteristic, and regardless of the structure of the memory cell, writing is performed using tunnel current flowing through a thin oxide film, which increases the total amount of charge that moves through the oxide film. As the number of electrons captured in the oxide film increases, the tunnel current decreases, and eventually writing and erasing becomes impossible, so there is an upper limit to the number of times that rewriting can be performed.

Furthermore, passing a tunnel current increases the defect density in the oxide film, leading to poor data retention.

[Problem that the invention attempts to solve 2] The above-mentioned conventional memory dedicated to bladder removal is all erased state 1.
Since the method is to write the write data 10- after setting the data to 11, even if the pre-fixed data is lOM and the write data is 10-, the erase and write currents from -〇1 → 111 → 101 will be changed. There is a problem with flowing through a thin oxide film.

SUMMARY OF THE INVENTION An object of the present invention is to provide a read-only memory in which erasing before writing can be selectively performed in accordance with written data.

[Means for solving inter-group points]

The read-only memory of the present invention includes a booster circuit that boosts the power supply voltage to a predetermined voltage value, and a data holding circuit that temporarily holds data to be written and outputs write data of the predetermined voltage value in response to a write instruction. , 1 according to the write instruction
a timer circuit that outputs a write timing signal in which the first half of the cycle is at a high level of the predetermined voltage value and the second half is at a low level; and a plurality of timer circuits arranged in rows and columns and into which the write timing signal is input to a control gate. The memory cell includes a cell array made up of memory cells, and a column selector and a row decoder that supply the write data to the drains of the selected memory cells.

[Example 1 Next, an example of the present invention will be described with reference to the drawings.

10 is a block diagram of an embodiment of the present invention.

The read-only memory shown in FIG.
The data holding circuit 2 outputs write data D0 to Di of pI), and the first half of one cycle is a voltage p
A timer circuit 3 outputs a write timing signal WT whose second half is at a low level while the second half is at a high level, and a plurality of timer circuits arranged in -5. A cell array 4 consisting of memory cells M6 to Mi and a memory cell M0 to which write data D, to Di are selected.
It is configured to include a column selector 5 and a row decoder 6 that supply data to the drains of ~'Mi.

Next, the operation of the read-only memory shown in FIG. 1 will be explained with reference to FIG. 2. FIG. 2 is a waveform diagram for explaining the operation of the read-only memory shown in FIG. 1.

In this embodiment, the memory cells M0 to Mi are of floating gate type, and are erased to the 11-state by applying a high potential to the control gate and a low potential to the drain. Writing is performed by applying a high potential to the drain, resulting in the 101 state. During filling and erasing, the sources of the memory cells M0 to Mi are set to floating.

Next, a word-by-word rewrite operation will be explained. After the data to be written is latched in the data holding circuit 2, the booster circuit 1 operates to boost the power supply voltage Vcc to a voltage VpI) that allows erasing and writing.

The timer circuit 3 consists of a timing signal generation circuit 31 and an inverter circuit 32, and the output signal of the timing signal generation circuit 31, which is generated in response to a write instruction, has a high level in the first half T'/2 and a high level 'I' in the second half of one cycle. /2 is a low level signal, and this signal is input to the inverter circuit 32 whose power source is voltage VPp. Therefore, the write timing signal WT output from the inverter circuit 32 has a first half T/2 at a high level of voltage Vpp. &, the second half T/2 becomes a low potential. Therefore, the potential applied to the control gates of the memory cells M0 to Mi of the cell array 4 is a high potential of voltage Vl)p in the first half T/2.

The second half T/2 becomes a low potential.

The data holding circuit 2 includes a data holding section 21 and an inverter circuit 22, and the data to be written held in the data holding section 21 is input to the inverter circuit 22 whose power source is the voltage Vl)P. Therefore, Vl from the data holding circuit 2
) Write data D0-Di having a voltage amplitude of p is output, passes through the column selector 5 and row decoder 6, and is applied to the drains of the selected memory cells M0-Mi.

In this case, in the first half T/2 of the write timing signal WT, the control gate of the memory cell to be erased is at Vl)p potential,
The drain becomes a low potential, and the memory cell to be written has a control gate at a Vl)I) potential and a drain at a Vl)p potential. Therefore, the memory cell to be erased is erased, but the memory cell to be written retains the previous data.

At the second half T'/2 of the write timing signal WT, the memory cell M. A low potential is applied to the control gate of -Ml.

Since the drain potential remains in the queen state, the control gate of the memory cell to be erased is at a low potential, the drain is at a low potential, and the erased data 111 is held. Writing is performed because the control gate of the memory cell to be written is at a low potential and the drain is at a pp potential. [Effects of the Invention] As explained above, the read-only memory of the present invention adds a timer circuit. By selectively performing erasing prior to data rewriting according to the written data, when rewriting a written memory cell, it is possible to retain the previous state without erasing it. This has the effect of increasing the number of times data can be rewritten in actual use.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a waveform diagram for explaining the operation of the read-only memory circuit shown in the figure. 1...boost circuit! ... Data holding circuit, 3 ... Timer circuit, 4 ... Cell array, 5 ... Column selector, 6 ... Row decoder, D0 ~Di...Write data, Mo~
M...Memory cell, WT...Write timing signal.

Claims (1)

[Claims] a booster circuit that boosts the power supply voltage to a predetermined voltage value; a data holding circuit that temporarily holds data to be written and outputs write data of the predetermined voltage value in response to a write instruction; a timer circuit that outputs a write timing signal in which the first half of the cycle is at a high level of the predetermined voltage value and the second half is at a low level; and a plurality of timer circuits arranged in rows and columns and into which the write timing signal is input to a control gate. A read-only memory comprising: a cell array of memory cells; and a column selector and a row decoder that supply the write data to the drains of the selected memory cells.