JPS6284972U - - Google Patents

Info

Publication number
JPS6284972U
JPS6284972U JP17687685U JP17687685U JPS6284972U JP S6284972 U JPS6284972 U JP S6284972U JP 17687685 U JP17687685 U JP 17687685U JP 17687685 U JP17687685 U JP 17687685U JP S6284972 U JPS6284972 U JP S6284972U
Authority
JP
Japan
Prior art keywords
via section
pattern
gap
obtaining
sides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17687685U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17687685U priority Critical patent/JPS6284972U/ja
Publication of JPS6284972U publication Critical patent/JPS6284972U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す断面図、第2図
は本考案の実施例を作成する基板を示す図、第3
図は従来のバイア部のみで接合した多層プリント
基板を示す図である。 第1図、第2図において、10は基板、11,
11′は導体パターン、12はバイア部、13は
ギヤツプを得るためのパターン、14,14′は
半田である。
Fig. 1 is a sectional view showing an embodiment of the present invention, Fig. 2 is a diagram showing a board for producing an embodiment of the present invention, and Fig. 3 is a sectional view showing an embodiment of the present invention.
The figure shows a conventional multilayer printed circuit board joined only by via portions. In FIGS. 1 and 2, 10 is a substrate, 11,
11' is a conductor pattern, 12 is a via portion, 13 is a pattern for obtaining a gap, and 14 and 14' are solder.

Claims (1)

【実用新案登録請求の範囲】 両面の導体パターン11,11′と、両面の導
体パターンの接続を行ない且つその表面に基板間
のギヤツプを得るためのパターン13を有するバ
イア部12とが形成された多数枚の基板10を、
前記バイア部12のみで半田接合して成る多層プ
リント基板において、 前記ギヤツプを得るためのパターン13は、そ
の直径がバイア部の直径より小さいことを特徴と
する多層プリント基板。
[Claims for Utility Model Registration] Conductor patterns 11 and 11' on both sides and a via section 12 having a pattern 13 on its surface for connecting the conductor patterns on both sides and for obtaining a gap between the boards are formed. A large number of substrates 10,
A multilayer printed circuit board formed by soldering only the via section 12, wherein the pattern 13 for obtaining the gap has a diameter smaller than the diameter of the via section.
JP17687685U 1985-11-19 1985-11-19 Pending JPS6284972U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17687685U JPS6284972U (en) 1985-11-19 1985-11-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17687685U JPS6284972U (en) 1985-11-19 1985-11-19

Publications (1)

Publication Number Publication Date
JPS6284972U true JPS6284972U (en) 1987-05-30

Family

ID=31117541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17687685U Pending JPS6284972U (en) 1985-11-19 1985-11-19

Country Status (1)

Country Link
JP (1) JPS6284972U (en)

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