JPS6285029U - - Google Patents
Info
- Publication number
- JPS6285029U JPS6285029U JP17656885U JP17656885U JPS6285029U JP S6285029 U JPS6285029 U JP S6285029U JP 17656885 U JP17656885 U JP 17656885U JP 17656885 U JP17656885 U JP 17656885U JP S6285029 U JPS6285029 U JP S6285029U
- Authority
- JP
- Japan
- Prior art keywords
- test
- signal
- digital
- analog
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Analogue/Digital Conversion (AREA)
Description
第１図ａ及び第１図ｂはこの考案の一実施例を
示す半導体試験装置の図で、第１図ａはそのブロ
ツク図、第１図ｂは試験台の構成図である。第２
図ａ及び第２図ｂは従来の半導体試験装置の図で
、第２図ａはそのブロツク図、第２図ｂは試験台
の構成図である。
図において、１５はＤ／Ａ変換器、１６はデジ
タルテスト信号、１７はアナログテスト信号、１
９はＡ／Ｄ変換器、２０はアナログ応答信号、２
１はデジタル応答信号、２２は試験台、２３は試
験装置本体である。なお、各図中同一符号は同一
、または相当部分を示すものである。
FIGS. 1a and 1b are diagrams of a semiconductor testing apparatus showing an embodiment of this invention, with FIG. 1a being a block diagram thereof, and FIG. 1b being a configuration diagram of a test stand. Second
FIGS. 2A and 2B are diagrams of a conventional semiconductor testing apparatus, FIG. 2A is a block diagram thereof, and FIG. 2B is a configuration diagram of a test stand. In the figure, 15 is a D/A converter, 16 is a digital test signal, 17 is an analog test signal, 1
9 is an A/D converter, 20 is an analog response signal, 2
1 is a digital response signal, 22 is a test stand, and 23 is a main body of the test device. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
スト信号を受けて、これをアナログ変換し、上記
半導体素子にアナログテスト信号を印加するＤ／
Ａ変換器、及び上記アナログテスト信号に基づき
、上記半導体素子から出力されるアナログ応答信
号を受けてこれをデジタル変換しデジタル応答信
号を出力するＡ／Ｄ変換器を有した上記半導体素
子装着用の試験台、この試験台とは離隔した位置
に設けられて上記試験台との間を電気接続線によ
り接続され、この電気接続線を通じて上記デジタ
ルテスト信号を出力するとともに、上記電気接続
線を通じて入力される上記デジタル応答信号を解
析する試験装置本体を備えた半導体試験装置。 A D/D converter receives a digital test signal for testing the characteristics of a semiconductor element, converts it into analog, and applies the analog test signal to the semiconductor element.
A converter, and an A/D converter for receiving an analog response signal output from the semiconductor element based on the analog test signal, converting it into a digital signal, and outputting a digital response signal. A test stand, which is provided at a location apart from the test stand and is connected to the test stand by an electrical connection line, through which the digital test signal is output, and which is input through the electric connection line. A semiconductor test device comprising a test device main body that analyzes the above-mentioned digital response signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17656885U JPS6285029U (en) | 1985-11-15 | 1985-11-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17656885U JPS6285029U (en) | 1985-11-15 | 1985-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6285029U true JPS6285029U (en) | 1987-05-30 |
Family
ID=31116933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17656885U Pending JPS6285029U (en) | 1985-11-15 | 1985-11-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6285029U (en) |
-
1985
- 1985-11-15 JP JP17656885U patent/JPS6285029U/ja active Pending