JPS6285332A - Arithmetic method for rule-based systems - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a control system that determines conditions and determines control commands according to the state of each equipment according to control logic described in rules, and This paper relates to a calculation method for a rule-based system that processes planning variables using production planning logic.

[Background of the invention]

In FA systems, production lines and operations are frequently changed as product life cycles become shorter and product types become more diverse. For this reason, prompt development and maintenance of institutional programs is required.

Conventionally, control programs have been developed using general-purpose languages such as FOR, TI(, AN, etc.).This method takes time to develop, understand, and change control programs.
- There was a problem that a specialized programming staff was required, and there was a drawback that the above-mentioned requirements could not be satisfactorily met. In contrast, “
``Equipment Group Control System'' (% Open/Close No. 59-163605, 1% Open/Close No. 59-205604). This method is called rule-based software, and the logic is written in arbitrary Japanese character strings in the ``rIF (condition), THEN (conclusion or action)'' type rule format (hereinafter referred to as IF-THEN rule or rule). Programs can be created simply by using this software, making it easy to develop programs and excel in understanding and modifying Theory 3J+. Here, in addition to the proposed method, A of the IF section
AN in the method uses a dedicated device f that executes processing of ND conditions.
I) A dedicated device that executes all the processes of φNote has a problem in that an enormous number of states must be stored in the content addressable memory device. Below, we will explain the operating principle of rule-based software and the operating principle of an already proposed arithmetic device that can process rules at crystal speed even when the number of rules is large.
This will be explained using diagrams and the problems will be explained.

FIG. 1 is a functional block diagram of the "equipment group control system".

11 is a rule storage section, 12 is a rule operation section, and 13 is a state storage section. Determining a control command using an IF-THEN rule involves sequentially repeating the process of using the conclusion of one rule to determine the conditions of another rule, and finally the action (control command) is written in the THEN part of the rule. This is performed on the principle that the conditions of the specified rules are satisfied and the index 1 command is determined. That is, at 2 in FIG. 1, the rule operation unit 12 retrieves the rules one by one from the rule storage unit 11 that stores the rules, and extracts the rules from the state storage unit 13 that stores the target state and the extracted rules. It is compared with the conditions of the IF part of the rule that has been set, and it is determined whether the conditions are satisfied. If the conditions are satisfied, the conclusion of the T HE N part of the extracted rule is added to the state storage unit 13. Here, in the condition judgment of the IF section, all the sentences (states) that match the sentences (conditions) of each IF stored in the IF section are
3, and further determines whether the variables (Xty,
z, etc.) For K, determine whether there is a value that simultaneously satisfies all the conditions described in the IF section (AND condition),
If it exists, generate that value.

FIG. 2 is a detailed diagram of the process in the apparatus shown in FIG. 1 when a variable is described in the parameter section of a rule.

21 to 25 are work tables within the rule operation section 12. In the rule storage unit 11, only one rule currently being processed (J4y, exported) by the rule operation unit 12 is shown. The rule operation unit 12 first
A match between the first IF character string "(A<X><Y>)" of the F part and the character string stored in the state storage section 13 is determined. The match determination at this time is performed using the part of the character string excluding the parameter part, that is, "(8)". If a matching character string exists in the status storage unit 13, the value of the parameter part in the matching character string is written in the corresponding parameter part of the IF character string, and the value of the variable is written to the work tape/
Import into I/21 (■). Furthermore, the rule operation unit 12 performs the same process on the next IF character string “(B<Z>kuY>)” and converts the value of the parameter part of the character string in the state storage unit 13 into the character string of the IF part. It is imported into another work table 22 as a variable value (■). After that, the variable values imported into both work tables 21 and 22 are combined to generate a variable value that satisfies the AND condition (the conditions in the IF part of the rule are treated as AND conditions), and the variables are transferred to another work table 23. Store (■) (This operation is called a JOIN operation, and will be referred to as such below as well). If there are three or more character strings in the IF part, the variable value is imported (■) for the next character string in the IF part, and the AND condition generated so far is satisfied with the imported variable value. Combines the variable values (in this case, those stored in the work table 23), includes the variable values just imported, generates a variable value that satisfies the AND condition, and stores it in the work table. Do (■).

This process is repeated for all character strings of the third or more IFs. After that, if there is a variable value that finally satisfies the AND condition, that value is added to the corresponding variable of the character string in the tTHTHEN section, and the value is added to the state storage section 1.
Add to 3 (■).

Arithmetic device for the already proposed rule-based system (Patent application 1986-1)
No. 2079) performs high-speed generation processing of variable values that satisfy the above AND condition. In this device, variable values are stored in a content addressable memory device CAM (hereinafter referred to as content addressable memory device CAM).
It is called. ) and use the parallel search function of CAM.
This is a method for quickly executing AND condition processing between multiple conditions. This will be explained using FIG. 41 is a normal storage device,
Reference numerals 42 and 43 designate a CAM, 44 a comparison section within the CAM, and 45 a dedicated circuit for row data overlapping for performing row data overlapping processing.

First, one of the work tables on which the JOIN operation is to be performed is stored in the normal storage device t41, and the other is stored in one CAM4.
2, respectively. Further, table data resulting from the JOIN operation is stored in another CAM 43. The operation is as follows.

That is, the table data is taken out line by line from the normal storage section [41] and used as search data for the CAM42 (at this time, data X and Z other than the common variable Y are masked). In the CAM 42, the comparison unit 44
Data comparison processing is performed simultaneously on all rows of table data in 42. The rows of the table in the CAM 42 where the values of the search data and the common data match are taken out one by one, superimposed on the search data by the dedicated circuit 45 for row data superimposition, and sequentially stored in another CAM 43! be done. In this device, by preparing two CAMs, in the rule of the rule-based software, there are three or more character strings that describe the conditions of the IF part, and the variable value that satisfies the AND condition just generated and the next When it is necessary to combine the imported new variable value with the IF condition and repeat the JOIN process again, by importing the new variable value into the storage device 41 and switching the roles of the CAMs 42 and 43 as appropriate. , JOIN operations can be executed continuously without data transfer. This has made it possible to execute rule processing in rule-based software at high speed.

However, in order to process a large amount of data at high speed with this method, a problem arises in that a large capacity memory cell and row data comparison hardware corresponding to the number of rows of the memory cell are required in the CAM42.43. It's here.

Therefore, there are problems in that the device becomes very expensive and large in size. In addition, in the rule-based software of the earlier application, in the process of generating variable values that satisfy the above-mentioned AND condition, in order to create all combinations of the data of the two imported work tables, the result of the JOIN operation is There is a possibility that the data to be stored will grow to the product of the data captured. Therefore, in order to prevent overflow, a historically large-scale CAM is required. On the other hand, A
In ND processing, the amount of data in the two work tables varies depending on the state of the object. Therefore, even if a CAM with a maximum capacity that does not overflow is prepared, problems such as inefficient use of FicAM have actually occurred.

[Purpose of the invention]

The purpose of the present invention is to eliminate such problems and to make a logical description method using rules that is highly readable, understandable, and easy to change applicable to objects that need to handle a large amount of state quantities. JOIN operation for large-volume work lr
The aim is to provide a computational method that can be used in the past at low cost.

[Summary of the invention]

Conventionally, the arithmetic unit of a rule-based system [(4'!j - Gansho 6
No. 0-12079) stored all data of one work table in one CAM, so a large-capacity CAM that would not overflow was required. Large capacity C
Even if you create a device using AM, the amount of data captured in CAM is not always large-volume work data (
The amount of data increases by combining two work tables, and decreases by combining AND items. ). Therefore, even if a large capacity CAM is used, the CAM
I cannot say that I am using it. Therefore, in this device, AN
By storing two work tables for removing sweat and one table for storing the results in three ordinary memories, and splitting the table for multi-leaf data, the process is relatively simple. Using small-scale CAM efficiently,
It is possible to perform AND processing. Next, the operating system of this device will be explained using FIG. 4.

In FIG. 4, 50 is a work table that is divided and processed, 51 is a work table that is extracted and processed one line at a time, and 52 is a work table that stores the results. Also, 53 is CAM.

45 is a row data superimposer (same as in FIG. 3) that superimposes matched data; 55 is a memory cell in the CAM;
56 is a search data register (
(Details will be described later). CAM on the work table 50
When data exceeding the capacity of the memory cell 55 in the memory cell 55 is fetched, work division processing as shown in FIG. 4 is performed. In the first division process, the data that will fit into the memory cells 55 in the CAM 53 are stored in the work table 50.
and sends it into the memory cell 55. Next, the first search data f, CA of work table 51
Send the search data in M 53 to 1/registration 56,
CAM 53 f: Activates and stores matched data in table 52 through all row data superimposers 54 . Next, the second row of data from the work table 51 is sent to the search register 56, CA and M2S are activated, and the results are stored in the table 52.

Continue this operation until the nth search! J! Shigaeshi CAM53
Activate. Next, for the second division process, the second division process data fiI remaining in the work table 50:
A new data is sent to the memory cell 55 in the cAM 53, the CAM 53 is activated for n pieces of search data, and the table 5 is
Store the result in 2. Similarly, work table 5
The division process is repeated t times until there is no 0 data. With the above data processing method, even when a large amount of work data is read, JOIN can be performed using a relatively small amount of CAM.
It becomes possible to perform calculations.

According to this method, the amount of data for performing JOIN operation is nn
, n lines, the processing time will be mxn if the processor f is not used, and m+n if a conventional arithmetic unit using two CAM's is used.

When the arithmetic device proposed in the present invention is used, the average number of times of division processing is α, which is proportional to αm + 2 n. The arithmetic device proposed in the present invention has two
Although the processing speed is slower than that using two CAMs,
If you know the amount of data that changes due to JOIN operation,
By determining the capacity of normal memory used as a work table and the capacity of CA and M, a relatively small capacity C
Using AM, one highly efficient JOIN calculation device can be installed in CA.

[Embodiments of the invention]

An embodiment of the present invention based on the above-mentioned principle will be described above with reference to the drawings.

FIG. 5 is a block diagram of a J OI N calculation device showing an embodiment of the present invention. This device is Memo IJ 1501
10. Memory 1150120. Memory 150130, C
AM502, internal data bus 504, internal address bus 505, external data bus 506, external address bus 50
7. Bus switching side (corporate) section 508, internal address generation section 5
10, external access index 1 section 509, table specification flag 511, mode flag 512, transfer end flag 512
0, memory data amount register 51310, 51320
, 51330, search data register 514, search result register 515, data superimposer 516, operation control unit 5
17, an IJ upper set 518, and other signal lines. Each part and signal line will be explained in detail below.

Internal data bus 504 and internal address bus 505
respectively, a pass line for data signals inside this device,
This is a pass line for address signals. In addition, the external data bus 506 and the external address bus 507 are connected to the memory 150110 and the memory 7750120 inside this device, respectively.
, a data signal for externally accessing the memory l[50130, CAM502, and other flag registers, etc.
This is a pass line for address signals.

This device has the ability to specify an address from the outside to the external address bus 507, read data on the external data bus 506 into the device, or read data inside the device onto the external data bus 506. There is an external access mode in which a large amount of work is divided according to the processing method shown in FIG. 4, and an internal operation mode in which a JOIN operation is automatically executed. To switch the mode, use the mode flag 51.
2. The mode flag 512 indicates an external access mode when it is ``θ'', and an internal operation mode when it is 1''.
It is set to "l" by latching 3t-= and is reset by the reset signal on the signal line 5004. Further, the state of the mode flag is sent to the signal line 5001. The normal mode flag is in the state of "0", indicating external access mode.

Bus switching control unit 508 switches external data bus 506 and external address bus 507 to internal data bus 504 and internal address bus 505, respectively, in external access mode in response to a signal on signal line 5001 indicating the state of mode flag 512. When in the internal operation mode, these are separated and the address signal line 500 of the internal address generation section 509 is connected.
6f, performs an operation of coupling to internal address bus 505;

In the internal operation mode, the internal address generation unit 509 stores memory 150110, memory [50120, memory ■5013
0. This is a part that generates an address for reading data in the CAM 502. Memory 150110, Memory [50
When the operation control unit 517 generates a control signal on the signal line 5005 specifying any one of the memory n150130, the register in the CAM 502, and the memory cell, it generates the corresponding address and sends it on the signal line 5006. Addresses are generated by sequentially accessing the memory cells of memory 150110, memory 1150120, memory 1J11150130, and CAM from the beginning of the address space. That is, as shown in FIG. 6, each time access to memory 150110, memory I[50120, memory 50130, and CAM 1502 is designated, the next generated address is incremented by the required amount. Further, for the registers in the CAM 502, addresses assigned to each register are generated. In addition, depending on the reset signal of the signal line 5007, the memory I 50110, the memory I 50120,
The generated addresses for the memory cells of the memory Ill'50130 and the CAM502 are reset to the beginning of the memory space.

Memo IJ I 50110, as shown in Figure 4,
It is used to store one work table 51 that performs OIN calculations. The data in the memory pointed to by the address signal on the address signal line 50081 is transferred to the control signal line 501.
It can be accessed through data signal line 50091 in response to a control signal on 01. Note that the in-memory data amount register 51310 indicates the number of lines in which data is actually stored in the work table 51 stored in the memo IJ150110. This register is connected to the internal data bus 504.
is set by latching the data to the latch signal on the signal line 50111 and through the signal line 50121. Also, the contents are signal 1i! 50131.

As shown in FIG.
This is for storing the table 50 and the work table 52 resulting from the JOIN operation. Memo!
Similarly to 7150110, data on internal data bus 504 is accessed through signal lines 50092 and 50093. In addition, signal lines 50082, 50102, 50112
, 50083°50103.50113 are the same as in the case of the memory 150110. Similarly to 51310, in-memory data registers 51320 and 51330 indicate the number of rows of data stored in memory 7750120 and memory 1l150130. In addition, the signal line 50
The meanings of 122°50132, 50123, and 50133 are the same as in the case of the in-memory data register 51320.

The CAM 502 is accessed using an address signal line 5014, a data signal line 5015, and a control signal line 5016, and at the same time, a reset signal line 5017, a search signal, and a [50
18. The associative search function is controlled by the search result signal line 5019. The associative search function of CAM will be explained with reference to FIG. FIG. 7 is a block diagram of registers within the CAM. The memory cell 63 stores data to be associatively searched. The mask data register 62 specifies a mask for a portion of the data in the search data register 61 that is not considered during a search. Mask data register 62
The data in the search data register 61 corresponding to the part where "0" is stored is masked and is not subject to data matching comparison during a search (only the part where "1" is stored is subject to comparison). The registers and memory cells are connected to signal lines 5014, 5015, and 501 like normal memory.
6. After storing data in these registers and memory cells, turn on the search signal line 5018.
By doing this, an associative search is performed. That is, among the data in the search data register 61 and the memory cell 63, a match comparison of the part designated as ``1'' in the mask data register 62 is performed simultaneously for all data in the memory cell 63, and the matched data is compared. 1'' is set in the search result 7 lag 64 corresponding to the row of the memory cell 63. If even one of the search result flags 64 is set to 1, this fact is indicated on the search result signal line 5019 and communicated to the outside.
If it does not rise, the signal line 5019 indicates that there are no search results. Further, the data in the memory cell 63 of the first row for which l" is set in the search result flag 64 is sent to the data signal [5015. Next, again, the search signal line 5
When 018 is turned on, search result 7 lag 64 and 2 scans ff1
The data in the memory cell 63 in the row where K"1" is set is sent to the data signal +15015, and the 7 lags in the first scan are erased. Note that by turning on the reset signal 5017, the contents of all memory cells are cleared.

The table specification flag 51 determines which of the memory 1150120 and the memory 71150130 is used for the work table 50 that performs the JOIN operation, and which is used for the work table 52 that stores the result of the JOIN operation.
Specified by 1. When this flag is 1″, memory [
Work table 5 for performing JOIN operation on 50120
50130 is used as the work table 52 for storing the result of the JOIN operation. ′
0”, the opposite is true.Table specification flag 51
1 is set by latching the latch signal on signal line 5020 and the signal on internal data bus 504 through signal line 5o21. Also, the contents are signal line 50
22.

The transfer end flag 512o is divided into a work table 50 (memory 50120) on which JOIN calculation processing is performed.
or memory llll50130) all data in C
Specify whether it is set in AM502. When this flag is 0'', it indicates that unprocessed data remains in the work table.

01'', all data in the work table is CA
Indicates that it is divided and set in M502. The transfer end flag 5120 is the latch signal 512 of the operation control unit 517.
3, it is set via the signal line 5121, and its contents are sent to the operation control section via the signal line 5121.

This flag is set by the operation control unit 517 on the signal line 512 before setting the mode flag 512 to 0'' (external operation mode).
It is set to '0'' through 1.

The external access control unit 510 includes the memory 150110, memory 150!20, and memory [7501] described above.
30, CAM502, mode flag 512, table specification 7 lag 511, data amount register in memory 51310
．． This is the part that controls access to 51320 and 51330 from the outside. In this part, the signals on the external address bus 507 are decoded, which of the above is to be accessed is determined, and the read/write of the signal i5023 is determined.
In response to the write signal, a control signal and a latch signal are sent to the access target. In addition, the external access control unit 510
At the end of the IN operation (mode flag 512 changes from ON to OFF)
(When the JOIN operation changes to F), an interrupt signal indicating the end of the JOIN operation is sent to the outside on the signal line 5024.

The search data register 514 is a register that retrieves and stores one row of data from the work table stored in the memory 150110. The search result register 515 performs an associative search between the data in the search data register 514 and the data in the memory cells in the CAM 502, and stores the matched data. Furthermore, the data in the search data register 514 and the search result data register 515 are sent to the data superimposer.
028°5027 is sent as im. These registers are set by the latch signal on signal line 5025 by latching the signal on internal data bus 504 through signal #5026. Its contents are sent on signals 1115027.5028, respectively. Further, in the search data register 514, by turning on the signal line 50282, the contents can be sent onto the internal data bus 504 through the signal line 50281.

The data superimposer 516 is connected to the search data register 514.
This is the part that superimposes the data in the search result data register 515 and the data in the search result data register 515. By superimposing the signals on signal lines 5027 and 5028, and using the timing signal on signal line 5029,
The superimposed resultant signal is sent out on signal #J5030.

The operation control section 517 is a section that controls the operation timing of each section described above and advances the JOIN calculation in the I operation mode. Mode flag 512, table specification flag 511 status, in-memory data amount register 513
According to the contents of 10, 51320 and 51330, the result of the associative search of the CAM 502 (the state of the search result signal line 5019), and the state of the transfer end flag 5120, signals are sent to other parts as appropriate to perform control. Note that the operation control unit 517 has an internal memory data amount counter 5171.
Count the amount of data resulting from the IN operation. This counter indicates the number of rows of data stored in the work table 52 that stores JOIN operation results. The contents of this counter are determined by specifying the address assigned to this register on the external address bus 507 in the external access mode and generating a read signal on the signal line 5023. 5172 and output to external data bus 506 through signal i5173.

The processing data amount counter 5132 is divided by the division Q shown in FIG.
+ is used when doing reasoning. memory 115
0120 or memory ■50130 data is CAM
Each time it is transferred to the memory cell 63 in 502, it is counted up. Still in memory data amount register 5132
When this counter becomes larger than 0 or the contents of 51330, the operation control unit 517 sets the transfer end flag 5120 to 1.
” (transfer complete).

The reset unit 518 is a part that sets the initial state of this JOIN calculation device, and uses a reset signal from an external reset signal line 5031 to reset the mode 7 lag 512 and the CAM50.
2. Generate a signal to reset the transfer end flag 5120.

Next, the operation of this embodiment will be explained using FIGS. 4 to 15. FIGS. 8 to 15 are diagrams showing data flows during operation of this embodiment. In the diagram, the number is 4.5.7
Please refer to the figure. Before starting the JOIN operation, the user first sends a reset signal to the signal line 5031 to set the initial state of the device. Depending on the reset signal, the reset section 518 sends an internal reset signal to the signal line 5017゜5.
004.5123, clears the memory cell 63 and flag 64 inside the CAM 502, and clears the mode flag 51.
2 is set to 0'' (FIG. 8 (2), hereinafter referred to as FIG. 8). Also, the transfer end flag 5120 is set to 0''. By setting the mode flag 512 to 0”K, bus switching 1RIJ (i11 section 508
, internal data bus 504 and external address bus 507
and an internal address bus 505, so that data can be set from outside. Next, the user stores the two work tables on which the JOIN operation is to be performed in the memory 1501.
10. Set in memory ■50120 (■, ■). The case where data to be subjected to a JOIN operation is set in the memory 1i 50120 and data as a result of the JOIN operation is set in the memory 1i 50130 will be described below. When the user sets the data to perform the JOIN operation, the user sets the number of rows set in the memory 1150120 in the memory data register 51310.5.
Set to 1320 (■.

■) Do. Setting to this register is performed by external access control section 510. That is, the data to be recorded is sent to external data bus 506, and the data is transmitted to internal data bus 504.

Furthermore, the data amount register in memory 513i0.51320
The address assigned to the external address bus 507
By setting the write signal to the signal @5023, the external access control unit 11 510 reads the memory 1501.
10 and memory [50m, signal line 50111.501 of data amount register 51310.51320 in memory of 20
A latch signal is generated on 12, and data on the internal data bus is taken in through all signal lines 5012J, 50122.

Note that the table designation 7 lag 511 and mode flag 512 are set from outside in exactly the same way. After setting the above, the user selects the joint 11 of the two sets to be JOIN operated.
11 Store data that masks variables other than the values (see explanation in Figure 3) in the mask data register 62 of the CAM 502. (In this case, memory ■5
0120) as the JOIN operation partner of the memory 150110 in the table specification flag 511), the mode flag 512 is set to 1'', and the internal operation mode is set. By setting the mode flag 512 to 1'', the bus The switching control unit 508 disconnects the external data bus 506 from the internal data bus 504 and the external address bus 507 from the internal address bus 505', and connects the signal line 5006 of the address signal generated by the internal address generating unit 509 to the internal address bus 505. Join. The operation control section 517 starts the operation of controlling the JOIN calculation when the signal on the signal line 5001 becomes 1'' (internal production mode, ■).The operation control section 517 first sends a reset signal to the signal line 5007. The internal address generating unit 509 is reset (see the explanation of the internal address generating unit above for details of the reset).
. Next, in order to set the data set in the memo IJll50120 to the memory cell in the CAM, operation assignment 1 is performed.
The unit 517 compares the capacity of the memory cell 63 (the number of rows of memory cells) specified in advance by the user with the in-memory datascape register 51320, and determines the number of rows of data to be set from the memory 50120 to the memory cells in the CAM 502. Number of rows of data for IJ 1150120 CAM5
02 (the one with the smaller number of rows of memory cells 63) is determined.

Then, the operation control unit 517 sends the address of the memory cell 63 in the CA-M2O3 through the signal line 50141, and also sends the address of the memory cell 63 in the CA-M2O3 to the internal address generation unit 509.
After generating the address of , one piece of work data for performing a JOIN operation is divided and set into memory cells in the CAM through the memory and internal data bus (Fig. 10).
(Figure 10 below). In addition, the processing counter 5132 in the operation control unit 517 is input from the memory [50120 to CAM50].
0) to count up the number of rows set in the memory cells in 2. The operation-specific N1 section 517 contains the contents of the processed data counter 5132 (memo processed within the CAM 502 +7
The number of rows of work data in Hs o 120) and the contents of the data amount register 51320 in memory are sent to signal IVj15.
0131, and when they match, the signal line 51
21, the transfer end flag f: "i" is set, and +v On is set when there is no match (that is, when data to be subjected to the JOIN operation remains in the memory 2).

After that, the operation control unit 517 executes the JO according to the procedure shown in FIG.
Perform an IN operation. That is, the data of the work table 51 stored in the memory 150110 is retrieved line by line from the beginning to Ilg, and the following process is repeated for the data a number of times specified by the in-memory data h1-register 51310. The operating side H+ unit 517 first clears the internal memory data amount counter 5171 to zero. Next, a signal specifying the memory 150110 is sent to the signal line 5005, and the internal address generation section 509 generates an address for accessing the memory 150110 (the address generation method is as described above in the internal address generation section 509).
09, see Akira). After that, a memory read control signal is generated on the signal line 50101, and the memo! 7150110
Reads the contents of one row of work table data stored in the internal data bus onto the internal data bus. The read data is latched by the search data register 514 through the signal line 5026 by sending a latch signal to the signal line 5025 of the search data register 514 (◎ in FIG. 11, hereinafter shown in FIG. 11). After that, the operation control unit 517 controls the signal line 5
0282, the contents of the search data register 514 are sent out again onto the internal data bus 504 through the signal line 50281.

The sent data is read into the search data register 61 in the CAM 502. That is, the operation control unit 517 sends a signal specifying the search data register 61 of the CAM 502 to the signal line 5005, and the internal address generation unit 50
9 generates an address for the search data register 61 of the CAIM 502, and captures it into the CAM 502 by sending a write signal to the signal IIM 5016 of the CAM 502 (
0).

That's all for memory 150110. The access procedures for memory ■50120, memory ■50130, CAM502, and other registers are the same, so descriptions thereof will be avoided.

After storing the data in the search data register 61 of the CAM 502, the operation control unit 517 transfers the data to the signal line 50 of the CAM 502.
18 to perform an associative search (12th
Figure 0, hereafter Figure 12). The operation control unit 517 repeats the following until the CAM search result signal (signal line 5019) turns OFF, and stores the JOIN operation result in the memory 1li5013.
Store it at 0. That is, the search signal (signal +Ij1
5018) are sequentially turned on, the search result data is sent onto the internal data bus 504, and latched in the search result register 515 (0). Thereafter, the contents of the search data register 514 and the contents of the search result register 515 are combined (◎) by the data superimposer 516, and a send signal is sent to the signal line 5029, thereby passing the entire signal line 5030 and transmitting the data. The superposition result is sent to internal data bus 504. The sent data is stored in order from the beginning of the memory [50130 (0). Note that the storage address is generated by the internal address generation unit 509 according to the procedure described above. Also, when data is stored, the in-memory data counter 5171 is counted up (0). The above operations are repeated at 1 when the search result signal (signal line 5019) turns OFF. Next, the operation control unit 517 transmits the data through the signal line 5121, and if the content of the transfer flag is θ'' (state B that J (divided unprocessed data to be subjected to JIN calculation remains) in the memory n50120, Send a reset signal to the CAM 502 through the signal line 5017, and clear the memory cell 63 and result search flag 64 in the CAM 502 (see FIG. 13 below).
Figure 13). Next, unprocessed data is transferred. ) The contents of the processed data amount counter 5132 are stored in the memory register 5.
If it is smaller than the value of 1320, the operation control section counts up the processing data amount counter (Q)L, sets the contents as the address of the memory 50120, and sets the internal address generation section 5.
09 to the internal address bus 505. On the other hand, the address of the memory cell 63 in the CAM 502 is determined by the operation control unit 517 through the signal line 50141.
502.

The addresses of the memory cells 63 are specified sequentially from the beginning of the memory cells 63. The data to be transferred is stored in the memory 115
0120 to the internal data bus 504 through the signal line 50092, and is sent to the CAM50 through the entire signal line 5015.
Data is sent to the memory cell 63 in 2. In this way, when the data is transferred and the memory cell 63 in the CAM 502 becomes full of data, the contents of the processed data amount counter 5132 are transferred to the in-memory register 513.
If the content of the memory becomes larger than the content of 20 (data amount of memory [50120]), the transfer will stop. In the latter case, the operation control unit 517 sets the transfer end flag 512 to "1" (transfer end) through the entire signal line 5121 ([phase]
). Once the data is set in the memory cell 63 in the CAM 502, the operation control unit 517 re-executes the JOIN operation according to the data processing method shown in FIG.
III50130 (FIG. 14).

As described above, the operations shown in FIGS. 13 and 14 are repeated until the operation control unit sets the transfer end flag to '1', and once all the work data in the memo IJ It 50120 has been processed, The operation control unit 517 sends the reset signal to the signal line 5017 of the CAM 502 and the signal line 500.
4 to clear the CAM 502 and mode flag 512.

(Fig. 15 01 et seq. Fig. 15). This makes it possible to access the inside of the device from the outside again. JOI
At the end of the N operation, the mode flag 512 changes from 1'' to “0”.
When the change occurs, the external access control unit 510 sends an interrupt signal to signal #5024 to be notified. If the calculation result is to be retrieved as is, it is sufficient to read from the outside the contents of the memory [750130 indicated by the table designation flag 511 for the number of rows indicated by the total memory data amount counter 5171. External reading 2 is controlled by the external access control unit 510 as described above. In addition, if three or more conditions are specified in the IP part of a rule in rule-based software and the JOIN operation must be executed again,
The data of the work table 51 that is imported from the outside for the first IF statement or more is stored in the memory by the user using the external access control unit 510, as shown in FIG.
Set to 0110. (Figure 15, ■). In addition, the memory data precious register 51310 (@)) and C
The amount of data in memory and the mask data are set in the mask data register 62 in the AM 502, respectively. and,
Specified 7 lugs 512 gold switching (“1” → “0”,
“0”→゛1”] By (O), the previous JOIN
The table 52 storing the calculation results is switched to the table 5 for performing the JOIN calculation, and the operations shown in FIGS. 9 to 14 are repeated. This allows any JOIN operation indicated by three or more IF statements to be performed.

In this embodiment, by dividing a large-capacity work table as shown in FIG. 4, even a relatively small-capacity content addressable memory device can utilize its parallel search function.

〔Effect of the invention〕

As explained above, according to the present invention, by using the parallel search function of the associative memory device and dividing one data table out of two work tables and storing data in the associative memory device, high-speed and large-capacity processing can be performed. An apparatus for processing work data can be provided. This makes it possible to process objects with a large number of leaf states in rule-based software, and improves readability using rules.

It is possible to apply this method to objects that require handling a large number of states using a logical description method that is highly understandable and highly variable.

[Brief explanation of drawings]

Fig. 1 is a functional configuration diagram of the rule-based software, Fig. 2 is an explanatory diagram of the rule processing of the rule-based software, Fig. 4 is an explanatory diagram of the JOIN calculation device, and Fig. 2 shows the JOIN calculation method of the present invention. 5 is a block configuration diagram of an embodiment of the present invention, FIG. 6 is an explanatory diagram of the memory space of this device, FIG. 7 is a configuration diagram of registers in the associative memory device, and FIGS. 8 to 15 is a data flow diagram showing the operation of the embodiment.

Claims (1)

[Claims] 1. A rule storage unit that stores rules consisting of conditions and conclusions for equipment groups; a status storage unit that stores the status of the equipment group, the content of work to be performed, and the content concluded by the rules; and the status of the equipment group. It has a rule operation unit that compares and matches the information stored in the storage unit with the conditions stored in the rule storage unit, and stores the conclusion of the rule in which the conditions are satisfied in the status storage unit, and controls the equipment group. In a rule-based system that determines commands, for two sets of data consisting of state storage information that match two sets of condition contents described in one of the above rules, the two sets are For the JOIN operation that creates set data consisting of all combinations of the above data that have the same value corresponding to the common item among the condition contents, two sets of input buffers that hold the respective data, JOI
It is equipped with an output buffer that holds and outputs the results of N operations, an associative memory device, and a data superimposition device that replaces the item value with a meaningful value from two data to create one data. Divide the data, store the divided data in the associative memory in order, take out the data one by one from another input buffer, use the data as search data, and use the search key for common items to associatively search the data in the associative memory. An arithmetic method for a rule-based system, characterized in that a JOIN operation is repeatedly executed by combining the retrieved data with a data superimposer and storing the result in an output buffer. 2. The calculation method of the rule-based system according to item 1, characterized in that the JOIN calculation is executed continuously while switching between the output buffer and one of the input buffers.