JPS6285468A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the integration of an element by providing a capacity increasing portion which extends in a depthwise direction of a substrate to increase a capacity between a control gate and a floating gate. CONSTITUTION:An N-type semiconductor substrate 10, an N-type source 20 and an N-type drain 30 formed separately in a P-well formed on the surface of the substrate 10, a channel region formed between the source 20 and the drain 30, a floating gate 50 covered through an insulating film on the channel region, and a control gate 60 covered through an insulating film above the gate 50 are composed. The gate 50 and the control gate 60 are integrally formed with channel opposed portions covered on the channel regions, and composed of capacity increasing portions 53, 63 extended in a plate shape in the depthwise direction of the channel regions and a channel stopper 70.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a floating gate type nonvolatile semiconductor memory device that enables area saving.

[Prior Art] In a conventional nonvolatile semiconductor memory device using a transistor with a floating gate, the usage of the floating gate and control gate is one of the factors that determines the degree of integration. In order to ensure the capacitance between each gate, a predetermined opposing area is required, but in reality, these gates are formed in a substantially planar arrangement. For this reason, the semiconductor substrate
However, there is a limit to the degree of aggregation of memory cells that store bit information, and the area occupied by these memory cells is large, making it difficult to achieve high integration.

Therefore, as described above, the present invention secures capacitance by extending a part of each of the floating gate and control gate in the vertical direction, and the non-volatile semiconductor has an element with an increased degree of integration. The purpose is to provide a storage device.

[Means for Solving the Problems] A non-volatile semiconductor memory device M (1) of the present invention, a semiconductor h (a source a3 and a drain installed on the surface of the plate separated from each other, and the source and drain A non-volatile device comprising a channel region formed between (: a channel region formed therein, a floating gate covering the channel region above the channel region via an insulating film, and a gate gate covering the channel region above the floating gate via an insulating film). In the 314 conductor memory device, the floating gate and the control gate number each have one of the channel regions.
A channel facing portion covering one side and the respective channel facing portions are integrally formed, and the substrate is configured to increase the capacitance between the control gate and the floating gate on at least one side of the channel region. The device is characterized by having a capacity increasing portion extending in the direction of the depth of the tube.

That is, the floating gates 1 and 1 of the memory wires constituting each memory cell of the non-volatile semiconductor memory '4 device of the present invention and the control gates are arranged in the thickness direction of the semiconductor substrate IIj! In other words, the capacity increasing portions are arranged in the vertical direction. Therefore, the area covered by each memory element on the surface becomes smaller, and the integration density becomes higher.

-3- The semiconductor substrate serving as the base material of the nonvolatile semiconductor storage device of the present invention may be either P type or N type. In the present invention, the conductivity type of the semiconductor substrate having the right majority carrier and the interpolated carrier is defined as the first conductivity type.

Impurity regions of a second conductivity type, which serve as a source and a drain, are formed spaced apart from each other on the surface of this semiconductor substrate. Here, the second conductivity type is a conductivity type having a different type of carrier from the first conductivity type. For example, when the first conductivity type is P type, the second conductivity type is N type.

Note that one or both of a first conductivity type well and a second conductivity type well may be formed on a first conductivity type semiconductor substrate. In this case, the source and drain must be formed on the surface of the well as impurity regions of a conductivity type containing carriers of a different type from those of the well.

The spacing, size, etc. between the source and drain may be within the range used for a normal memory element.

The part of the substrate surface between the impurities constituting the source and drain, or the surface part of this well if a trench is formed, is the channel part floating gate. It is formed in an insulator 1 installed on one side (deep and vertical with respect to the substrate).

In the present invention, the gate portion above the channel is referred to as the channel opposing portion, and the gate portion on the side of the channel is referred to as the capacitance increasing portion.

The channel facing portion is the portion that primarily exerts electrostatic influence, such as the channel depletion layer. The capacitance increase section mainly defines the capacitance of the floating gate and the LllIII gate. The channel facing part has an insulating film (
For example, the control gate is formed as a channel facing part of the control gate formed with an oxide film in between, and a control gate facing part formed above the channel with an insulating film having a thickness of 1 in the same manner.

Depending on this thickness t, the device may be an electrically erasable FEROM or an EPR that can be erased by ultraviolet light.
It can be set as OM.

In other words, when the thickness t is 50 to 200, the device is EFR
When operating as an OM and the thickness t is between 500 and 1000, the device operates as an EPROM.

The capacitance increasing portion is formed on the side of the channel with a thick insulating film having a thickness of 0.5 μm or more in between. Channels 1 to 1 are in contact with the insulating film surrounding this capacitance increasing portion.
A brim is formed. This capacitance increase can also be formed on both sides of the channel. The shape of the capacitance increasing portion and its location (whether it is formed on one side or both sides of the channel) can be arbitrarily determined depending on the required capacitance of the floating gate and control gate.

The control gate can also be a common control gate capacitively coupled to two or more floating gates depending on the arrangement of each storage element.

In order to isolate each storage element from other storage elements, the source, drain, and channel constituting one storage element are formed by diffusing impurities of a conductivity type different from that of the impurity regions constituting these sources and trains. Must be isolated with a stopper.

−〇 − The device of the present invention (1) Formed and cut by the following method.Usually,
A source region of a first conductivity type, a drain region of a first conductivity type, and a channel region of a second conductivity type are formed in a well of a second conductivity type formed in this semiconductor II plate of a first conductivity type. In order to form the volume increasing portion, which is a feature of the present invention, first, in this second S'#i-type tube, other steps are performed, such as a mask process for forming a transistor part, a mask process for forming a diffusion layer, and a process for forming a mask for a transistor part, a mask process for forming a diffusion layer, and a mask process for forming a mask for a transistor part, a mask process for forming a diffusion layer, and a mask process for forming a mask for a transistor part, a mask process for forming a diffusion layer, and a mask process for forming a mask for a transistor part. Prior to each step of the mask process, holes or grooves are formed in the depth direction for forming and covering a predetermined container. This hole (hole) contributes to each gate of a plurality of transistors, rather than to each gate of a plurality of transistors, when viewed from the substrate surface. A band-like formation that spreads out is desirable. Also, the depth of this hole or groove can be designed according to the needs and capacity. Note that this depth t does not have to be uniform over the entire hole or height, and may vary from place to place depending on the corresponding gates 1 to 1 of the transistors.

After this opening or vortex is formed, a conventional transistor masking process, a diffusion layer masking process, and a partial masking process are sequentially performed to manufacture the device of the present invention. i4 can do it.

[Operation] In the nonvolatile semiconductor memory device of the present invention, the so-called "writing" which changes the conductive state between the source and the drain is similar to the operation in a normal EPROM. In other words,
For example, it is preferable to apply a positive voltage to the control gate adjacent to the train and the floating gate to charge the floating gate, which has a storage expansion section in the deep direction. Since this floating gate is entirely surrounded by an insulating film, carriers in the floating gate do not escape (they are retained in the floating gate).

[Examples] Hereinafter, the present invention will be explained in detail based on specific examples.

In the nonvolatile semiconductor memory device of the present invention, the positional relationship of the drain, source, control gate, etc. in its main parts is shown in FIGS. 1 and 2. Of these, Figure 1 shows the two-dimensional positional relationship and has a plan view C, and Figure 2 shows the Δ-
It is a sectional view seen from the direction of arrow A.

This device includes an N-type semiconductor substrate 10, an N-type source 20 and an N-type drain 30, which are provided in a P-well provided on the surface of the substrate 10 and separated from each other. A channel region (not shown) formed between the drains 30, a floating gate 50 covering the channel region and above through an insulating film, and a control gate covering above the floating gate 1-50 through an insulating film. gate 60, this floating game].50 and the control game 1-
Reference numerals 60 refer to a channel opposing portion covering the upper side of the channel region, a capacity increasing portion 53, 63, and a channel stopper, which are formed integrally with the respective channel opposing portions and extend in a plate shape toward the depth of the channel region. 70.

The nonvolatile semiconductor memory device of this embodiment has the above configuration.

Since this non-volatile semiconductor storage device can be manufactured using conventionally used well-known technology, a detailed explanation of the manufacturing process will be omitted. It can be manufactured by performing the steps sequentially. That is, this nonvolatile semiconductor memory device includes a step of forming a groove 17 in a P-well 13 formed in a semiconductor substrate 10 having a silicon nitride film 15 and a thermal oxide film 16 formed on the surface thereof, and selective oxide films 16 and 19.
A process of forming a channel 1-flange 70, a process of filling the polysilicon film 50 into this groove 17, a process of selectively etching the polysilicon film 50, a process of forming a thermal oxide film 18 on this polysilicon film 50, and The process of forming a polysilicon film 60 that will become a control gate on the oxide film 18, this polysilicon! ]! The step of etching the I 60 and the step of forming the source/drain 20, 23, 25, 35 are sequentially performed. The completed state is the 8th
Shown in cross-section in the figure.

The device formed as described above is used as an EPROM. Its operation is similar to that of conventional devices, and writing can be achieved by charging the floating gate.

According to this embodiment, by providing a control gate with a capacitance increasing portion extending toward the depth of the substrate and a floating gate = -1~, a non-volatile semiconductor memory device with improved integration density is realized. can. Further, by providing a control gate for each channel region, it is possible to simultaneously write to the devices formed by these channel regions.

[Effects of the Invention] According to the present invention, in a non-volatile semiconductor memory device constituted by an element having a source, a drain, a floating gate, and a control gate, the capacitance of the floating gate and the control gate is increased in the deep direction of the semiconductor substrate. By providing the capacitance increasing portion that extends to the area, the degree of integration of the element can be improved.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing the main parts of a nonvolatile semiconductor memory device according to a specific embodiment of the present invention, and FIG.
3 to 9 are cross-sectional views showing the bottom part of the device at each major T step when manufacturing the nonvolatile semiconductor memory device of the first embodiment, and FIG. Figure 11-4 is a cross-sectional view when selective diffusion and thermal oxide film are formed.
Figure 5 is a cross-sectional view when a polysilicon film is formed;
The figure shows a cross-sectional view of a polysilicon film selectively etched, FIG. 7 shows a cross-sectional view of a polysilicon film forming a control gate, and FIG. 8 shows a polysilicon film selectively etched. FIG. 10... Semiconductor substrate 20... Source 30...
・Drain 40...Channel region 50...
・Floating gate 60... Control gate patent applicant
Nippondenso Co., Ltd. Sokujin Ben J1-1- Hiroma Okawa
Patent Attorney Akio Maruyama Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] (1) A source and a drain provided on the surface of a semiconductor substrate in isolation from each other, a channel region formed between the source and the drain, and a floating gate covering the channel region above with an insulating film interposed therebetween; In a nonvolatile semiconductor memory device comprising a control gate covering above the floating gate with an insulating film interposed therebetween, the floating gate and the control gate each have a channel opposing portion covering above the channel region and a channel opposing portion covering the channel region. The capacitance increasing portion is formed integrally with the substrate and extends toward the depth of the substrate so as to increase the capacitance between the control gate and the floating gate on at least one side of the channel region. Characteristic non-volatile semiconductor memory device.