JPS6285535A - Serial transmission system for binary data - Google Patents

Abstract

PURPOSE:To minimize the data being in out-of-frame synchronization by transmitting the input binary data as the start signal a 3-cycle frame signal and a 1-cycle reverse signal and sending one of both halves of a bit as the data and the other half as the 2-round data respectively. CONSTITUTION:A timing generating counter 11 receives the transmission control signal CTL and the oscillation signal P0 of an oscillator 12 and produces pulses P1 and P2 and a serial transmission flag SDF. Then data D0, D1-D7 are given to a register 13 through parallel input lines ch.1-ch.8 together with the pulse P1 applied to a clock input terminal CK. The outputs D0-D7 are sent to a parallel/serial converting circuit 15 together with the parity bit PR produced by a parity generator 14 directly or via an inverter. Then the outputs D0-D7 and the bit PR are outputted successively through a terminal SXP under the control of the timing of the flag SDF. Then the frame signal containing three cycles of the same value and the 1-cyclestart signal obtained by inverting said frame signal are transmitted. Then one of both halves of a bit is delivered as the data value with the other half delivered as the inverted 2-cycle data.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention applies to asynchronous serial transmission of binary data.
This invention relates to a binary data serial transmission system that facilitates frame synchronization.

"Prior Art" FIG. 7 is an explanatory diagram showing an example of a conventional asynchronous serial data transmission system.

For example, when transmitting binary data that takes H and L level signal values divided into 8 bits, in the asynchronous serial data transmission method, the level of the ND transmission line when there is no signal, for example, the H level, is different from the level. The 1-bit start bit STB is converted into 8 data bits Do, D+,...
..., D? After the 8-bit data and parity bit PR, a stop bit SPB of a level different from the start bit STB level, that is, the same level as the ND level when there is no signal, is added. and transmit it.

On the receiving side, the signal on the transmission path is detected, and when it detects that the signal changes from the H level of ND when there is no signal to the L level of the start bit STB, the following 8-bit data Do+D++... ..., D, and parity bit PR. Parity Pino) There is a stop bit SPB at H level after PR, and at that H level,
Just like that, 1 level of ND continues when there is no signal. The 8-bit data of the next frame also has an L level start pitch) S
Since TB is transmitted, 8-bit data is fetched using the same procedure.

``Problems to be Solved by the Invention'' In the method shown in FIG. 7, when each frame is transmitted discontinuously, there is no gap between the H level stop bit SPB and the start bit STB of the next frame. The H level signal period NO is inserted, so that a sufficiently long [I level signal period is maintained between one frame and the next frame. However, if data transmission is performed continuously, the no-signal period ND disappears. Therefore, immediately after the H level stop bit SPB, the L level start bit STB of the next frame is sent. In this case, as shown in FIG. 8, the L-period (2) immediately follows the 1-bit H-period (2).

By the way, the receiving side does not always have a ready response system that can detect the signal on the transmission path and process the reception before data starts to be sent.In other words, due to some reason on the receiving side, the signal on the transmission path The start of detection may be delayed and the start bit STB■ of the first frame may not be detected. Moreover, when the next frame is sent consecutively following the first frame, the star) bit ST[1 is the length of 1 bit, and as shown in FIG. The start bit STB of the next frame which changes between l, -jlJJ and other data bits D. .

Dr...D? It is not possible to distinguish between.

Therefore, in the conventional frame synchronization method, the start bit S of the first frame of consecutively transmitted frames is
If frame synchronization is lost in TB, it will not be possible to synchronize the frames of the signals transmitted thereafter.
For this reason, the continuity of serial data is interrupted and frame synchronization cannot be achieved until a no-signal period ND occurs.
Any data sent up to that point will be lost.

"Means for Solving the Problems" In the present invention, the frame structure is such that even if signals are transmitted continuously, frame synchronization can be achieved for each frame. Therefore, even if data is being sent continuously, frame synchronization can be achieved immediately from the next frame when monitoring is started, and therefore lost data can be minimized.

That is, in the present invention, each data bit is composed of two time units, that is, a first period t1 and a second period t2, and at the beginning of each frame of input binary data, a frame signal FMS consisting of three periods of the same value is generated. This is followed by a one-cycle start signal ST obtained by inverting the frame signal FMS, and then binary data is generated for each bit of the first cycle t1 of that data value (or that data). The second period tt is converted into two-period data in which the data value is inverted (or the data value), and the data is transmitted and received.

"Operation" In the transmission method of this invention, each data bit has two frequencies f.
'J]t+, tz, but the signal level is inverted in the two periods (converted to No. 3 and transmitted. In other words, the data bit with a data value of 1 is transmitted in the first and second periods. 1
．． ．． 1. For example, if it is converted into a (H, L) signal and transmitted, the data bit with a data value of O is (L, H)
It is converted into a signal and transmitted. Therefore, the data 1.1 of two consecutive vias ) Di, Dial is converted into four periods of HlL, H, L signals, as shown in Figure 1.
The continuous 2-bit DJ-07+1 1.0 signal is converted into H, L, L, H signals as shown in FIG. In this way, if a 1-bit signal is composed of two periods and the signal levels of the two periods are inverted, the signal level will not be held at the same level for three consecutive periods. Therefore, when transmitting 24fi data, the receiving side can detect the beginning of a frame by sending a three-cycle L (or H)-level frame signal FMS at the beginning of the frame. Furthermore, by sending a one-cycle H (or L)-level start signal ST, which is inverted from the frame signal FMS indicating frame data capture timing, from the transmitting side, the receiving side can know the frame data capture timing. I can do it.

Embodiment FIG. 3 is a diagram showing a frame structure according to the binary data serial transmission system of the present invention. In the present invention, the unit of signal processing time for transmission or reception is expressed as one cycle, and in this example, the data transmitted in one frame is 8 bits.

That is, in the present invention, a frame signal FMS having a constant level of three cycles leads each frame in order to identify the start of each frame. In Figure 3, the frame signal FMS with three periods
is held at L-level.

Following this L-level frame signal FMS, an H-level start signal S which is inverted from the frame signal FMS
T continues for one period.

In this embodiment, after three periods of frame signal FMS and one period of start signal ST, 8-bit data bit D o
, D+, Dz, . . . , Dy are transmitted, and one parity bit PR is further added. Each data bit D a,, D +, D t,...
・, Dt and parity bit PR are all in the first period t
The level of No. 13 is reversed between 1 and the second period [2.

Therefore, as shown in FIGS. 1 and 2, except for the frame signal FMS period, I (and L level signals) never last for more than three periods.

FIG. 4 is a diagram showing an example of a circuit configuration on the transmitting side in the transmission system according to the present invention.

The timing generation counter 11 receives a transmission control signal CTL,
The oscillation signal P, a h from the oscillator 12 is given, and the first
．． Second pulse PI, P2 and serial transmission flag SDF
occurs. The register 13 has a parallel data input line ch+
8-bit data D o, D +, D z, ... through +et+z+ctls+...+chs
, D7, and the clock input terminal C are supplied with the first pulse P, and at the timing of the rise of the first pulse P, the 8-bit transmission data D0゜Dt, Dz, . . . , D is input to the input terminal. Read from and output from the output terminal. These outputs Do, D+ of register 13.

Dt, . . . , Dt are supplied to a parity generator 14, and the parity generator 14 outputs predetermined parity bits PR for the 8-bit data Do, DI, Dz, .

On the other hand, the first...third parallel data input terminals I5. of the parallel-to-serial conversion circuit 15. ...+F has L level signal, 4th
The parallel data input terminal ■4 is given a signal of level ■(), and each data bit D output from the register 13 is
o, D+, Dz,..., Dq and parity bit Pl? are applied to the parallel-to-serial conversion circuit 15 directly and via an inverter 16, respectively. That is, 5th, 7th.・
....

19 odd number parallel data input terminals Is+ If+...
・,■8. contains 8-bit data D e, D I+
Dz, . . . , Dt are each in the first period 1. 13 of
Parallel data input terminals of even numbers of 6th, 8°..., 20! 6. I8. ....

■At 2°, data D o, D I + D t,...
, D] inverted signal D o/, D I7. Dt
/, ..., D7/ are given as the respective second period t2 signals, and the 21.22nd parallel data input terminal ix+,
I! ! is the parity bit pH and its inverted signal P
R/ is the first period 1. and is given as a signal with a second period t2. These data are read into the parallel-to-serial conversion circuit 15 at the timing of the second pulse P2. Subsequently, the serial transmission flag SDF from the timing generation circuit 11 becomes H. This H serial transmission flag SD
In response to F, the parallel-to-serial conversion circuit 15 transfers the read data to the sending end SXP side, one pulse per I pulse of the second pulse P2.
The signals are shifted one by one and outputted sequentially from the sending end SXP. Therefore, the sending end SXP initially outputs L, L, and H signals, and then the signal D0. of the first period t of the first bit Do. As the signal of the second cycle Mtt of the first bit D0, the inverted signal DO/ of Do, the j-th cycle t of the second bit Dt
1 signal DI, its second round! 'Jltz signals are output in the order of inverted signals D1/, . . . , and finally the first parity bit. 2nd round tl, L□ signal Pit,
PI? / is output and transmission of one frame of signals is completed. Further, if there is data for transmission, the data is supplied to the register 13, and the transmission control signal CT1. is given to the timing generation counter II, and the next frame is transmitted.

FIG. 5 is a diagram showing an example of a circuit configuration for explaining the signal processing operation on the receiving side in the transmission system according to the present invention, and FIG. 6 is a diagram showing the operation timing of the circuit in FIG. 5.

Next, the main operation of this circuit will be explained. The oscillator 21 is 1
The sample timing generation circuit 22 and the frame detection circuit 2 output an oscillation signal CK having a period of 178.
Supply to 3. The sample timing generation circuit 22 divides the frequency of this oscillation signal CK and outputs a received signal sampling clock CK and a read clock CL having eight times the period, and sends them to the serial-parallel conversion circuit 25 and the clock terminal CK of the register 26. supply

On the other hand, the received signal 11X sent from the transmitting side is received by the frame detection circuit 23. It is supplied to a flip-flop 24 and a serial-parallel conversion circuit 25. The frame detection circuit 23 is 3
This circuit detects that the periodic frame signal FMS continues. This frame detection circuit 23 receives the received signal RX via the NOR gate GI to the clear terminal CL, and outputs the oscillation signal C only while the clear terminal CL is held at H. 8 clocks x 2.5 cycles = 20
When the clock is counted, a positive signal is output from the output terminal Q. This positive signal is supplied to the OR gate G2, and its output S1 is supplied to the clear terminal C1 of the flip-flop 24 as a clear signal S via the AND gate G3 and the OR gate G4 to clear the flip-flop 24. In other words, the flip-flop 24 receives the frame signal FMS.
I remember that the mouth came three times. Also, or gate G
The output S1 of 2 clears the frame detection circuit 23 itself through the NOR gate G.

A reception signal RX is given to the clock terminal CK of the flip-flop 24, and at the rising edge of the start signal ST in the signal, the signal H(,) of the data terminal is taken in and the start flag S, Output as .

This start flag S is given to the enable terminal E of the sample timing generation circuit 22 and the serial-to-parallel conversion circuit 25, and the sample timing generation circuit 22 and the series-to-parallel conversion circuit 25 are put into an operating state by this No. 13 S. , the serial-to-parallel conversion circuit 25 receives the timing clock CK+ from the sample timing generation circuit 22, and outputs its serial data input terminal I.

The received signal RX supplied to the
In the example of FIG. 6, the data value of the first bit D0 is 1, and the first and second periods 1. ．． 1. This is an example in which the signals H and L of the second pit (Dr) are read, then the signal of the data value O of the second pit (Dr) is read, and finally the parity pin 1-PR (=O) is read.

The received signal taken into the serial-parallel conversion circuit 25 is part 1.
It is output from the 8-tree parallel output terminal IP and supplied to the register 26. The serial-parallel conversion circuit 25 converts the 8-bit data D1. D,,D! , ..., D, and parity bit r'l? Each of the first. Second period t, signal DO, D, /, Dl, 1) +/, Dz, Dz8 ・
...,D.

After completing the acquisition of D78 pH and PII/, the sample timing generation circuit 22 transfers the clock CK to the register 2.
6 and their data Do, Do/, Dl, D+
To eight Z, D, eight =', Dy+ Dt/, PR,
PR/ is read into register 26. Further, the clock CK clears the flip-flop 24 as a clear signal S2 with respect to the OR gate G4. As a result, the start signal S disappears (L), and the serial-parallel conversion circuit 25
stops reading the received signal RX from the serial data input terminal I.

The output signal of the register 26 is given to a data check circuit 27, and the presence or absence of a parity error is checked.This data check circuit 27 performs a predetermined parity check and compares the odd-numbered data D t i -l with the next even-numbered data. The values of the th data Dti, that is, the first period and the second period of each bit, are compared, and it is also checked that these values are different. If these tests are correct, a continuation permission signal S is output from the data test circuit 27 and supplied to the AND gate G.

When this read permission signal S4 is present, the clock CK.

The data read clock CK is supplied from the AND gate Gs to the output register 28 at the timing when the flip-flop 24 is cleared. At the timing of this read clock CKj, the output register 28 is transferred to register 2.
6 output signals D o, D +, D t, ..., D
, read.

``Effects of the Invention'' The frame synchronization method using the conventional asynchronous serial data transmission method requires a frame synchronization detection signal with a minimum length of 3 bits, and when data is sent continuously, the frame synchronization The detection signal has a length of l bits,
Frame synchronization could not be achieved and the transmitted data was lost. However, according to the present invention, data of 1 bit length is stored in the first . If the first period is a true data period or a pseudo data period, the signal obtained by inverting the first period signal is a pseudo data period or a true data period, and At the beginning of each frame, a frame signal for three periods and a start signal for one period obtained by inverting the frame signal were provided to constitute a frame. By having such a frame configuration,
Frame synchronization can be established from any next frame of continuously transmitted data.

Therefore, it is possible to minimize the loss of transmitted data due to failure to achieve frame synchronization. Furthermore, the signal processing circuit required for this purpose is simple, and compared to conventional systems, there is no increase in redundant signal periods due to the frame configuration, and there is no drop in transmission efficiency.

In this example, the first . Although both values of the second period are read into the serial-parallel conversion circuit 25, it may be configured such that only the value of one of the periods is read.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of data conversion according to the present invention, and FIG. 2 is a diagram showing a case where two consecutive data 1 and l are converted, and FIG. 2 is a diagram showing a case where data 1.0 is converted. Third
4 is a diagram showing an example of a data transmitting circuit of this invention. FIG. 5 is a diagram showing an example of a data receiving circuit of this invention. 6 is a diagram showing a timing chart of the receiving circuit shown in FIG. 5, FIG. 7 is a diagram showing a conventional frame structure, and FIG.
The figure is a diagram showing a data string on a transmission path when data is continuously sent using the frame structure shown in FIG. 7. 11: Timing generation circuit, 12: Oscillator, 13: Input register, 14: Verity generator, 15: 8-column-to-serial conversion circuit, 16: Inverter, 2■: Oscillator, 2
2: Sample timing generation circuit, 23: Frame detection circuit, 24: Friab flop, 25: Serial-to-parallel conversion circuit, 26: Register, 27: Data inspection circuit, 28:
Output register, G+,..., G,: Gate circuit. Patent applicant Japan Aviation Electronics Industry, Ltd. Representative
people grass fields plants
1 drawing 2 drawings and a half 3 drawings

Claims (1)

[Claims] (1) At the beginning of each frame of input binary data, a frame signal consisting of three periods of the same value is transmitted, followed by a start signal of one period which is an inversion of the frame signal, and the following input 2 Value data, for each bit,
A binary data serial transmission method that converts one half of the data into two-cycle data, the other half of which is the inverted value, and transmits the data.