JPS628571A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS628571A JPS628571A JP60147849A JP14784985A JPS628571A JP S628571 A JPS628571 A JP S628571A JP 60147849 A JP60147849 A JP 60147849A JP 14784985 A JP14784985 A JP 14784985A JP S628571 A JPS628571 A JP S628571A
- Authority
- JP
- Japan
- Prior art keywords
- type
- base region
- layer
- semiconductor layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/156—Drain regions of DMOS transistors
- H10D62/157—Impurity concentrations or distributions
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電力用ＭＯＳ型電界効果トランジスタ（以下、
パワーＭＯＳ’ＦＥＴと称する）を有する半導体装置に
関し、特にバ”−ＭＯＳＦＥＴの微細化とともに、高耐
圧化、オン抵抗の低減を図った半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power MOS field effect transistor (hereinafter referred to as
The present invention relates to a semiconductor device having a power MOSFET (referred to as a power MOS'FET), and particularly to a semiconductor device in which miniaturization of a power MOSFET, high breakdown voltage, and reduction in on-resistance are achieved.
従来のパワーＭＯＳ Ｆ ＥＴは、第２図に示すように
、一の導電型の半導体基板２１上にこれと同じ導電型の
半導体層２２を積層し、この半導体層２２の主面に逆の
導電型のベース領域２３を形成し、さらにこの中に一の
導電型のソース領域２４を形成している。そして、半導
体Ｎ２２の上にはゲート絶縁膜２５を介してゲート電極
２６を形成し、このゲート電極２６直下の前記ベース領
域２３をチャネル領域２７として構成している。As shown in FIG. 2, a conventional power MOS FET has a semiconductor layer 22 of the same conductivity type stacked on a semiconductor substrate 21 of one conductivity type, and a semiconductor layer 22 of the opposite conductivity type on the main surface of this semiconductor layer 22. A base region 23 of the type is formed, and a source region 24 of one conductivity type is further formed therein. A gate electrode 26 is formed on the semiconductor N22 via a gate insulating film 25, and the base region 23 directly under the gate electrode 26 is configured as a channel region 27.
このパワーＭＯＳ Ｆ ＥＴによれば、ベース領域２３
に対してゲート電極２６に印加される電圧に応じてチャ
ネル領域２７が導通、遮断される。導通状態では、電流
はソース電極２８−ソース領域２４−チャネル領域２７
−半導体層２２−半導体基板２１を通って流れる。また
、遮断状態では、ベース領域２３と半導体層２２との間
に逆バイアスが印加される。図中、２９は眉間絶縁膜で
ある。According to this power MOS FET, the base region 23
The channel region 27 is turned on or off depending on the voltage applied to the gate electrode 26. In the conductive state, current flows between source electrode 28 - source region 24 - channel region 27
- semiconductor layer 22 - flows through semiconductor substrate 21; Further, in the cut-off state, a reverse bias is applied between the base region 23 and the semiconductor layer 22. In the figure, 29 is an insulating film between the eyebrows.
上述した従来のパワーＭＯＳ Ｆ ＥＴは、遮断状態の
とき、ソース領域２４、ベース領域２３および半導体層
２２（半導体基板２１）からなるＰＮＰ又はＮＰＮバイ
ポーラトランジスタに逆バイアスが印加され、この際ベ
ース領域２３ではソース領域２４の下部において電流が
流れ、この電流によりソース領域２４とベース領域２３
で形成される接合が順バイアスされる。このため、ベー
ス領域２３内でキャリア密度が増大し、ついには耐圧を
維持できなくなる場合があった。これを避けるには、ベ
ース領域２３の抵抗を下げる必要があり、−例としては
ベース領域２３をソース領域２４に対して十分に深く形
成すればよい。しかしながら、通常ベース領域２３、ソ
ース領域２４はゲート電極２６をマスクとした２重の不
純物注入方法によって形成しているため、ベース領域２
３を深く形成すると、これとともに横方向に領域が拡大
され、この結果チャネル領域２７の長さくチャネル長）
が長くなり、パワーＭＯＳＦＥＴの微細化、ひいては低
コスト実現のための障害となる。In the conventional power MOS FET described above, when in the cut-off state, a reverse bias is applied to the PNP or NPN bipolar transistor consisting of the source region 24, the base region 23, and the semiconductor layer 22 (semiconductor substrate 21), and at this time, the base region 23 In this case, a current flows under the source region 24, and this current causes the source region 24 and the base region 23 to
The junction formed by is forward biased. For this reason, the carrier density increases within the base region 23, and it may become impossible to maintain the breakdown voltage. To avoid this, it is necessary to lower the resistance of the base region 23; for example, the base region 23 may be formed sufficiently deep relative to the source region 24. However, since the base region 23 and the source region 24 are usually formed by a double impurity implantation method using the gate electrode 26 as a mask, the base region 23 and the source region 24 are
3 is formed deeply, the area is expanded in the lateral direction, and as a result, the length of the channel region 27 (channel length) is increased.
becomes long, which becomes an obstacle to miniaturization of power MOSFETs and furthermore to realization of low cost.
本発明の半導体装置は、パワーＭＯＳ Ｆ ＥＴの微細
化を図るとともにその耐圧を向上するために、ベース領
域を浅く形成する一方でベース領域の下にこれと同一導
電型の埋込層を形成し、かつゲート電極直下の半導体層
にはこれと同一導電型の高湯度埋込層を形成した構成を
有している。In the semiconductor device of the present invention, in order to miniaturize the power MOSFET and improve its breakdown voltage, the base region is formed shallowly, and a buried layer of the same conductivity type as the base region is formed under the base region. , and has a structure in which a high-temperature buried layer of the same conductivity type is formed in the semiconductor layer directly below the gate electrode.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明のパワーＭＯＳ Ｆ ＥＴの断面図であ
り、一の導電型、ここではＮ型半導体基ｖｉｌ上に厚さ
〜１５μｍのＮ型半導体Ｎ２を積層し、このＮ型半導体
層２の主面に深さ〜２μｍのＰ型ベース領域３およびそ
の上に深さ〜１μｍのＮ型ソース領域４を夫々形成して
いる。そして、Ｎ型半導体層２の上面には二酸化シリコ
ン等のゲート絶縁膜５を厚さ〜５００人で形成し、その
上に多結晶シリコンからなるゲート電極６を厚さ〜０．
５μｍで形成している。更に、その上に厚さ〜１μｍの
眉間絶縁膜９を形成し、この眉間絶縁膜９に開設したコ
ンタクト孔を通して前記ソース領域４に接続するソース
電極８を形成している。FIG. 1 is a cross-sectional view of the power MOS FET of the present invention, in which an N-type semiconductor N2 with a thickness of ~15 μm is laminated on one conductivity type, in this case, an N-type semiconductor substrate vil. A P-type base region 3 with a depth of 2 μm and an N-type source region 4 with a depth of 1 μm are formed on the main surface of the substrate. Then, on the upper surface of the N-type semiconductor layer 2, a gate insulating film 5 made of silicon dioxide or the like is formed to a thickness of ~500 mm, and a gate electrode 6 made of polycrystalline silicon is formed thereon to a thickness of ~0.0 mm.
It is formed with a thickness of 5 μm. Furthermore, a glabellar insulating film 9 having a thickness of 1 μm is formed thereon, and a source electrode 8 connected to the source region 4 through a contact hole formed in the glabellar insulating film 9 is formed.
一方、前記ベース領域３の下側には、ベース領域３と同
一導電型、つまりＰ型の埋込層１１を深さ〜５μｍで形
成している。また、前記ゲート電極６直下位置の前記Ｎ
型半導体基板ｌとＮ型半導体層２との境界部には、これ
らと同一導電型でかつ不純物濃度の高いＮ型埋込層１２
を深さ〜５μｍで形成している。なお、この構成ではチ
ャネル領域７の長さは１μｍ程度である。On the other hand, below the base region 3, a buried layer 11 of the same conductivity type as the base region 3, that is, P type, is formed to a depth of 5 μm. Further, the N at a position directly below the gate electrode 6
At the boundary between the type semiconductor substrate l and the N type semiconductor layer 2, there is an N type buried layer 12 having the same conductivity type as these and having a high impurity concentration.
is formed with a depth of ~5 μm. Note that in this configuration, the length of the channel region 7 is about 1 μm.
以上の構成によれば、ベース領域３は自身の深さを大き
くしなくても、下側に形成したＰ型埋込層１１の作用に
よって実質的にその深さが大きくされ、その抵抗が低減
される。これにより、チャネル７が長くされることなく
、つまり素子の微細化を図った上でベース領域３の抵抗
を低減し、遮断状態におけるソース領域４とベース領域
３との間の順バイアスを解消し、耐圧を高く保つことが
できる。According to the above structure, the depth of the base region 3 is substantially increased by the action of the P-type buried layer 11 formed below without increasing its own depth, and its resistance is reduced. be done. As a result, the resistance of the base region 3 can be reduced without lengthening the channel 7, that is, the element can be miniaturized, and the forward bias between the source region 4 and the base region 3 in the cut-off state can be eliminated. , can maintain high pressure resistance.
一方、Ｐ型埋込層１１を形成することにより、Ｐ型埋込
層１１と半導体基板１との距離Ｌａが、従来におけるベ
ース領域と半導体基板との距離Ｌｂ（第２図参照）より
も低減されるため、耐圧を維持するためには距離Ｌａを
Ｌｂ程度に設定する必要がある。このため、半導体層２
を従来よりも厚く形成することになるが、これではチャ
ネル導通状態におけるチャネル領域７から半導体基板１
に到る電流路が長くなり、オン抵抗が増大することにな
る。しかしながら、本発明では半導体層２に形成した高
濃度のＮ型埋込層１２の作用により実質的な電流路を短
縮でき、オン抵抗を少なくとも従来以下に低減すること
ができる。On the other hand, by forming the P-type buried layer 11, the distance La between the P-type buried layer 11 and the semiconductor substrate 1 is reduced compared to the conventional distance Lb between the base region and the semiconductor substrate (see FIG. 2). Therefore, in order to maintain the withstand voltage, it is necessary to set the distance La to approximately Lb. Therefore, the semiconductor layer 2
is formed thicker than before, but this means that the channel region 7 in the channel conduction state is separated from the semiconductor substrate 1.
The current path to reach becomes longer, and the on-resistance increases. However, in the present invention, the substantial current path can be shortened due to the action of the heavily doped N-type buried layer 12 formed in the semiconductor layer 2, and the on-resistance can be reduced at least to a level lower than that of the conventional semiconductor layer.
本実施例の半導体装置によれば、従来構造の耐圧６０ｖ
５オン抵抗０．１Ω（ｉＪパ”） ＭＯＳＦＥＴを、
その特性を損なうことなく、しかも素子サイズを６０％
に縮小することが達成できた。According to the semiconductor device of this embodiment, the breakdown voltage of the conventional structure is 60V.
5 On-resistance 0.1Ω (iJ Pa”) MOSFET,
Without compromising its characteristics, the element size has been reduced by 60%.
It was possible to reduce the size to
ここで、半導体基板１、半導体層２はもとよりベース領
域３やソース領３１ｉ４の導電型は互いに逆の導電型で
構成してもよい。Here, the conductivity types of the semiconductor substrate 1, the semiconductor layer 2, the base region 3, and the source region 31i4 may be opposite to each other.
以上説明したように本発明は、パワーＭＯＳＦＥＴのベ
ース領域を浅く形成する一方でベース領域の下にこれと
同一導電型の埋込層を形成し、かつゲート電極直下の半
導体層にはこれと同一導電型の高濃度埋込層を形成した
構成としているので、チャネル長を長くすることなくベ
ース領域の低抵抗化を図って耐圧を向上するとともに、
半導体層の電流路の短縮化を図ってオン抵抗を低減でき
、更に素子の微細化を達成することができる。As explained above, the present invention forms a shallow base region of a power MOSFET, forms a buried layer of the same conductivity type under the base region, and forms a buried layer of the same conductivity type in the semiconductor layer directly under the gate electrode. Since it has a structure in which a conductive type high-concentration buried layer is formed, the resistance of the base region is lowered without increasing the channel length, and the breakdown voltage is improved.
The on-resistance can be reduced by shortening the current path in the semiconductor layer, and further miniaturization of the device can be achieved.
第１図は本発明のパワーＭＯＳ Ｆ ＥＴの断面図、第
２図は従来のパワーＭＯＳ Ｆ ＥＴの断面図である。
１．２１・・・半導体基板、２．２２・・・半導体層、
３．２３・・・ベース領域、４．２４・・・ソース領域
、５．２５・・・ゲート絶縁膜、６．２６・・・ゲート
電極、７．２７・・・チャネル領域、８．２８・・・ソ
ース電極、９．２９・・・層間絶縁膜、１１・・・Ｐ型
埋込層、１２第２図FIG. 1 is a sectional view of a power MOS FET of the present invention, and FIG. 2 is a sectional view of a conventional power MOS FET. 1.21...Semiconductor substrate, 2.22...Semiconductor layer,
3.23... Base region, 4.24... Source region, 5.25... Gate insulating film, 6.26... Gate electrode, 7.27... Channel region, 8.28... ... Source electrode, 9.29 ... Interlayer insulating film, 11 ... P-type buried layer, 12 Fig. 2
Claims (1)
体層を形成し、この半導体層内に逆の導電型のベース領
域を形成し、さらにこの領域内に一の導電型のソース領
域を形成し、かつ前記半導体層上にゲート電極を配設し
たＭＯＳ型電界効果トランジスタを有し、前記ベース領
域を浅く形成する一方でベース領域の下にこれと同一導
電型の埋込層を形成し、かつ前記ゲート電極直下の前記
半導体層にはこれと同一導電型の高濃度埋込層を形成し
たことを特徴とする半導体装置。1. A semiconductor layer of the same conductivity type is formed on a semiconductor substrate of one conductivity type, a base region of the opposite conductivity type is formed in this semiconductor layer, and a source region of one conductivity type is further formed in this region. and has a gate electrode disposed on the semiconductor layer, the base region is formed shallowly, and a buried layer of the same conductivity type as the base region is formed under the base region. A semiconductor device characterized in that a high concentration buried layer having the same conductivity type as the semiconductor layer is formed in the semiconductor layer immediately below the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60147849A JPS628571A (en) | 1985-07-04 | 1985-07-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60147849A JPS628571A (en) | 1985-07-04 | 1985-07-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS628571A true JPS628571A (en) | 1987-01-16 |
Family
ID=15439643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60147849A Pending JPS628571A (en) | 1985-07-04 | 1985-07-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS628571A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01300569A (en) * | 1988-05-27 | 1989-12-05 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0423719U (en) * | 1990-06-18 | 1992-02-26 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5742164A (en) * | 1980-08-27 | 1982-03-09 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-07-04 JP JP60147849A patent/JPS628571A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5742164A (en) * | 1980-08-27 | 1982-03-09 | Hitachi Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01300569A (en) * | 1988-05-27 | 1989-12-05 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0423719U (en) * | 1990-06-18 | 1992-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR920005513B1 (en) | A semiconductor device having a structure in which parasitic transistors are difficult to operate and a method of manufacturing the same | |
| JPH05198800A (en) | Insulated gate bipolar transistor | |
| JPH0357614B2 (en) | ||
| JP2003508919A (en) | Lateral thin-film SOIPMOS device having drain extension region | |
| JPS6237545B2 (en) | ||
| JPH0575110A (en) | Semiconductor device | |
| JPH11274495A (en) | Vdmos transistor | |
| JP2000269487A (en) | Semiconductor device and manufacturing method thereof | |
| JPH0786580A (en) | High voltage semiconductor device | |
| JP3522532B2 (en) | Semiconductor device | |
| JPS6180858A (en) | Power mosfet | |
| JP3161091B2 (en) | Semiconductor integrated circuit device | |
| JP3211529B2 (en) | Vertical MIS transistor | |
| JPS628571A (en) | Semiconductor device | |
| JPH09246545A (en) | Power semiconductor device | |
| JPH0555594A (en) | Vertical field effect transistor | |
| JPH1174517A (en) | Semiconductor device | |
| JPH08213618A (en) | Semiconductor device | |
| JP2526960B2 (en) | Conduction modulation type MOSFET | |
| JPH07176731A (en) | Vertical insulated gate field effect transistor | |
| JP2924348B2 (en) | Transistor | |
| JP2629437B2 (en) | Lateral insulated gate bipolar transistor | |
| JP2502696B2 (en) | Semiconductor integrated circuit device | |
| JPH06334120A (en) | Semiconductor device | |
| JPH01134974A (en) | Vertical mosfet |