JPS628594Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to the improvement of electronic counting circuits composed of ICs (integrated circuits) and the like.

FIG. 1 shows a conventionally commonly used counting circuit, which is comprised of counters 11 ₁ to 11 ₄ , a multiplexer 12 , a scan counter 13 , and a scan clock generator 14 . Each of the above counters 11 ₁ to 11 ₄ is a decimal 1.
It is a digit counter. Therefore, the counting circuit in FIG. 1 is a counting circuit for four decimal digits. Further, the multiplexer 12 and the scan counter 13 are used to reduce the number of wirings from this counting circuit to the outside. In other words, if you want to take out the output of each digit in parallel to the outside as is, 4 digits x 4 =
Although 16 output lines are required, if the scan counter 13 and multiplexer 12 are used to time-divisionally scan the output digit by digit, the first
As shown in the figure, there are four BCDs (Binary coded
decimal) output lines 14 ₁ to 14 ₄ and four digit output lines 15 ₁ to 15 ₅ .

FIGS. 2a to 2f are timing charts showing the operation of the counting circuit configured as described above, and as is clear from the figures, the output is scanned and extracted digit by digit in a time-division manner.

Although such a counting circuit has been widely used in the past, this type of counting circuit is not advantageous in terms of power consumption. That is, in this counting circuit, it is necessary to drive the multiplexer 12 in order to sequentially time-divide the count output digit by digit and output it to the outside, and for this purpose, a scan counter 13 and a scan clock generator 14 are required. These scan counters 1
3. Power consumption increases due to the operation of the scan clock generator 14. In particular, in general counting displays, the count content and display content must always match, so
The scan counter and scan clock generator must be operated constantly, and their clock operation increases power consumption.

On the other hand, in recent years, when converting a counting circuit to an IC,
CMOS (ComPlementary MOS) IC technology has been used. This CMOS IC has the great feature that almost no current flows in a static state (a state in which the logic state inside the IC is not inverted). In addition, it is required that the output (count value) of the counting circuit can be displayed as is, and recently it has become possible to display it on an LCD.
(liquid crystal) is widely used. Therefore, the power consumption of this display portion is also becoming significantly smaller.

Considering the above points, it is natural that it is necessary to further reduce the power consumption of the counting circuit itself, and there has been a strong demand for improvements to reduce the power consumption of the counting circuit.

This idea was made in view of the above points,
The object of the present invention is to provide a counting circuit that can reduce power consumption.

An embodiment of this invention will be described below with reference to the drawings. FIG. 3 shows a counting circuit according to an embodiment of this invention, and the same parts as in FIG. 1 are designated by the same reference numerals. Therefore, the explanation of the overlapping parts will be omitted. The difference between the counting circuit of this invention and the conventional one lies in the way the scan clock generator 14 is controlled.

That is, scan clock generator 14 is controlled by count _input signals input to counters _111-114 . That is, the scan clock generator 14 is driven by the set output of the flip-flop 15, which is set by the counting input signal.

FIG. 4 is a timing chart showing the operation of the counting circuit shown in FIG. 3, and a in the figure shows a counting input signal. When this count input signal is input, the flip-flop 15 enters the set state (FIG. 4b),
This set signal is applied to scan clock generator 14. As a result, the scan clock generator 14 generates a clock pulse as shown in FIG. 4c and supplies it to the scan counter 13. In synchronization with this clock pulse, the scan counter 13 generates digit signals _T1 to _T4 as shown in FIG. 4d to g, and also generates a reset signal as shown in FIG. 4h.
Generate TR. This reset signal TR is BCD
This reset signal TR resets the flip-flop 15, thereby stopping the clock generation operation of the scan clock generator 14. and,
When the next count input signal is input, the flip-flop 15 again enters the set state and performs the same operation as described above.

As described above, when there is no count input signal, the scan clock generator 14 is in a non-operating state.
The scan clock generator 14 is activated only when a count input signal is received, that is, when the contents of the counter change. This results in
Because scan clock generator 14 consumes power only when a count input signal is received, overall power consumption is significantly reduced.

Note that in order to operate as described above, a latch circuit is required in the display circuit portion, but since the latch circuit is generally attached to the display drive circuit, no inconvenience occurs. Figure 5 is a diagram showing a display circuit connected to the counter circuit of this invention shown in Figure 3, where 21 is the counting circuit of this invention shown in Figure 3, and 22 is an LCD (liquid crystal) display section, 2
3 is a drive circuit for the display section 22, which includes an LCD decoder/driver 23a and a latch circuit 23b.

As explained above, according to this invention, the scan clock generator and scan counter are always kept inactive, and only when a count input signal is input, this count input signal is used to control the scan clock generator and scan counter. , it is possible to provide a counting circuit that can significantly reduce power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional counting circuit, FIGS. 2 a-f are timing charts showing its operation, FIG. 3 is a block diagram showing a counting circuit according to an embodiment of the invention, and FIGS. 4 a-f i is a timing chart showing the operation of the same embodiment, and FIG. 5 is a configuration diagram when a display circuit section is connected to the counting circuit of the same embodiment. 11 ₁ to 11 ₄ ... counter, 12 ... multiplexer, 13 ... scan counter, 14 ...
Scan clock generator, 15... flip-flop.

Claims (1)

[Scope of utility model registration request] A counting device that time-divisionally outputs a count value for each digit includes a plurality of counters provided corresponding to each digit, a multiplexer connected to the output stage of these counters, and a scan counter that controls the multiplexer. and a clock generator that provides a scan clock to this scan counter.
A counting circuit comprising means for starting the clock generator at the input timing of a counting input signal, and stopping the starting after sending out a predetermined number of clock pulses.