JPS628644A - Line protocol discriminating device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a line protocol determination device for a modem interface used in videotex and the like.

BACKGROUND OF THE INVENTION Due to the remarkable progress in semiconductor technology in recent years, Videotex, which has been used in the professional field, is now being widely used by general users. However, even when general users access the same database, it is necessary to use different line protocols depending on the data communication networks used. Particularly in the United States, when accessing the Videotex database using a Ba1l 212m modem, two types of transmission protocols can be used: asynchronous data transmission and synchronous data transmission such as CCITTX and 25LAPB. However, there is a strong desire for a line protocol discrimination device that allows the terminal itself to automatically discriminate the line protocol simply by making a telephone call to the network.

Hereinafter, a conventionally used line protocol discriminating device will be explained with reference to the drawings.

FIG. 3 is a block diagram of a conventional line protocol discriminator. In the figure, reference numeral 3a indicates an input line for receiving signals from the other party's station via the telephone line.

31 is a demodulation circuit that demodulates the received signal on the input line 3a and converts it into digital data. 32 is a synchronous/asynchronous conversion circuit which receives the output of the demodulation circuit 31 as an input, and converts synchronous demodulated data of the demodulation circuit 31 into asynchronous data when the other station performs asynchronous data transmission. 3
3 is an asynchronous communication interface circuit operated when performing asynchronous communication. 34 is a synchronous communication interface circuit operated when performing synchronous communication.

36 is a synchronous/asynchronous conversion circuit that converts input asynchronous data into synchronous data when the own station performs asynchronous data transmission. 36 is a modulation circuit that modulates the output of the synchronous/asynchronous conversion circuit 36.

3b is an output line for a transmission signal which is an output signal of the modulation circuit 36. 37 is synchronized with the synchronous/asynchronous conversion circuit 32;
This is a switch for connecting the asynchronous conversion circuit 35 to the asynchronous communication interface circuit 33 or to the synchronous communication interface circuit 34. 38 is a switch 37. Synchronous/asynchronous conversion circuit 32. This is a control circuit that controls the synchronous/asynchronous conversion circuit 36. 39 is a microcomputer, and an asynchronous communication interface circuit 33. It controls the synchronous communication interface circuit 34 and the control circuit 38.

The operation of the line protocol discriminating device configured as described above will be explained below.

When a user accesses a data communication network and it is unclear at this point whether the line protocol is asynchronous data transmission or synchronous data transmission, the microcomputer 39 assumes that the transmission is asynchronous data transmission and controls the control circuit 38. via the synchronous/asynchronous conversion circuit 32 and the synchronous/asynchronous conversion circuit 3
5 is turned on, and at the same time, the switch 37 is switched on so that the asynchronous communication interface circuit 33 switches between the synchronous/asynchronous conversion circuits 32 and 35.
Switch so that you can connect with.

After that, when the other station performs synchronous data transmission, the received signal on the input line 3& is demodulated by the demodulation circuit 31,
As the output 3d of the demodulation circuit 31, continuous flags as shown in FIG. 4 are generated. This flag consists of 1-bit logic 0 data, 6-bit logic 1 data, and 1-bit logic 0 data. 3d signal is synchronized/
Since the synchronous/asynchronous conversion circuit 32 is on at this point, the output 3C of the synchronous/asynchronous conversion circuit 32 is subjected to synchronous/asynchronous conversion, and the output 3C of the synchronous/asynchronous conversion circuit 32 is input to the asynchronous conversion circuit 32. The waveform shown in B is output. That is, the output 3C regards the signal 41 as a start bit and outputs the signal 47, recognizes the signal 42 as an 8-bit character and outputs the signal 48, and outputs the stop bit 49 because there is no stop bit immediately after the flag 42. It automatically outputs signal 43 as a start bit and outputs signal 50 (start bit), treats signal 44 as an 8-bit character and outputs signal 51, and treats signal 45 as a stop bit and outputs signal 62. The signal 46 is regarded as a mark state, and a signal 53 in a mark state that is shorter by the amount corrected for the time shift caused by the stop pit automatically inserted in the signal 49 is output. From then on, the above process is repeated.

Therefore, the 3C signal is serial-parallel converted by the asynchronous communication interface circuit 33 via the switch 37.

The microcomputer 39 recognizes the 48 characters in FIG. 4 as "7K" (hexadecimal representation) and the 61 characters as "3F" (hexadecimal representation).

Therefore, by setting the time T and the number n appropriately, when the microcomputer 39 detects the combination of data 7IC ('i hexadecimal expression) and 3F (hexadecimal expression) n or more times within time T from the start of data reception, , the microcomputer 39 determines that the other station will perform synchronous data transmission. Then, the microcomputer 39 controls the control circuit 3.
8, the synchronous/asynchronous conversion circuit 32 and the synchronous/asynchronous conversion circuit 36 are turned off, the switch 37 is switched off, and the synchronous communication interface circuit 34 is switched off to the synchronous/asynchronous conversion circuit 32.
and the synchronous/asynchronous conversion circuit 36. Thereafter, reception is performed by a demodulation circuit 31, a synchronous/asynchronous conversion circuit 32 . Transmission is performed via the synchronous communication interface circuit 34, and transmission is performed via the synchronous communication interface circuit 34. Synchronous/asynchronous conversion circuit 36. This is done via the modulation circuit 36.

Furthermore, when the combination of data 7E (hexadecimal representation) and 3F (hexadecimal representation) can be detected less than n times within time T, asynchronous data transmission is continued. In this case, reception is performed by the demodulation circuit 31. Synchronous/asynchronous conversion circuit 32. Transmission is performed via the asynchronous communication interface circuit 33, and the asynchronous communication interface circuit 33.synchronous/asynchronous conversion circuit 35. This is done via the modulation circuit 36.

Problems to be Solved by the Invention However, the above configuration has the following problems. In other words, when the other station performs asynchronous data transmission and starts communication, 7]K (hexadecimal representation) and 3F(
When a combination of data (hexadecimal representation) is transmitted many times, it may be mistakenly determined to be synchronous data communication even though it is actually asynchronous data transmission.

In view of the above problems, the present invention provides a line protocol discrimination device that can more reliably discriminate between asynchronous data transmission and synchronous data transmission.

Means for Solving the Problems In order to achieve this object, the line protocol discrimination device of the present invention is provided with two control circuits arranged between the microcomputer, the synchronous/asynchronous conversion circuit, and the switch. , a synchronous/asynchronous conversion circuit for transmission and a synchronous/asynchronous conversion circuit for reception.
A first control circuit that controls the asynchronous conversion circuit, a synchronous/asynchronous conversion circuit for transmission, and a synchronous/asynchronous conversion circuit for reception are connected to either an asynchronous communication interface circuit or a synchronous communication interface circuit. By providing a second control circuit that controls the switch, two types of control can be performed independently.

According to the present invention, a control circuit for controlling the synchronous/asynchronous conversion circuit and a control circuit for controlling the switching device are each provided independently, and when it is unclear whether synchronous data transmission or asynchronous data transmission is required, the synchronous/asynchronous for reception By stopping the conversion operation of the conversion circuit, applying the demodulated data as it is to the conversion circuit and the interface circuit via the switch, and making a determination using this data, it is possible to accurately determine whether synchronous data transmission or asynchronous data transmission occurs. It can be carried out.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a line protocol discrimination device according to an embodiment of the present invention. 3 in the diagram
a is a reception signal line, 31 is a demodulation circuit, 32 is a synchronous/asynchronous conversion circuit for reception, 33 is an asynchronous communication interface circuit, 34 is a synchronous communication interface circuit,
36 is a synchronous/asynchronous conversion circuit for transmission, 36 is a modulation circuit, 3b is a transmission signal line, 37 is a switch, and the above is the third
The configuration is the same as the one shown in the figure.

Reference numeral 11 denotes a first control circuit that controls whether or not to operate the synchronous/asynchronous conversion circuit 32 for reception and the synchronous/asynchronous conversion circuit 35 for transmission. 12 controls a switch 37 that connects the reception synchronous/asynchronous conversion circuit 32 and the transmission synchronous/asynchronous conversion circuit 35 to either the asynchronous communication interface circuit 33 or the synchronous communication interface circuit 34. This is a second control circuit.

The operation of the line protocol discriminating device configured as described above will be explained below with reference to FIG. 2.

First, if a user accesses a data communication network and at this point the line protocol is determined to be either asynchronous data transmission or synchronous data transmission, the microcomputer 39 assumes that the transmission is asynchronous data transmission, and control circuit 12
The switch 37 is switched so that the asynchronous communication interface circuit 33 is connected to the synchronous/asynchronous conversion circuits 32 and 36 via. At the same time, the microcomputer 39
turns off the synchronous/asynchronous conversion circuits 32 and 35 via the first control circuit 11 (no conversion operation is performed).
. Thereafter, when the other station performs synchronous data transmission, the received signal on the input line 3& is demodulated by the demodulation circuit 31, and continuous flags as shown in FIG. 2 are generated as the output 3d of the demodulation circuit 31. The 3d signal is input to the synchronous/asynchronous conversion circuit 32, but since the synchronous/asynchronous conversion circuit 32 is off at this point, the synchronous/asynchronous conversion circuit 32
The same waveform as 3d is outputted as the output signal 3C. Therefore, the signal 30 is input to the asynchronous communication interface circuit 33 via the switch 37.

The asynchronous communication interface circuit 33 receives a 3C signal,
That is, the waveform in FIG. 2 is interpreted as follows. 21 is the start bit, 22 is the 8-bit character without the stop bit, 23 is the next start bit, 24 is the next 8-bit character, 26 is the stop bit, 2
6 is recognized as a mark state. Therefore, the microcomputer 39 can recognize the waveform shown in FIG. 2 as follows.

In other words, the part 22 has a framing error of 7.
It was recognized as data with the value K" (hexadecimal representation), and the 24 part did not cause a framing error °"3F''
It is recognized as value data (in hexadecimal representation). From then on, this process is repeated.

Therefore, the time T and the number n are set appropriately as in the case of the conventional example, and the microcomputer 39 detects that a framing error has occurred within the time T from the start of data reception.
” (hexadecimal representation) and +t 3fl 79 (1cs representation) that did not cause a 7raming error n times or more, the microcomputer 39 determines that the other station will perform synchronous data transmission. And the second
The synchronous communication interface circuit 34 connects the switch 37 via the control circuit 12 to the synchronous/asynchronous conversion circuit 32.3.
5 and start synchronous data transmission. In this case, reception is performed by the demodulation circuit 31. Synchronous/asynchronous conversion circuit 32. Transmission is performed via the synchronous communication interface circuit 34, and transmission is performed via the synchronous communication interface circuit 34.
．． This is done via a synchronous/asynchronous conversion circuit 36 and a modulation circuit 36.

Still a framing error occurred °t 7 K t-
When the combination of data "(hexadecimal expression)" and "3F" (hexadecimal expression) that does not cause a framing error is detected less than n times within time T, asynchronous data transmission is continued. At this time, the microcomputer 39 turns on the synchronous/asynchronous conversion circuits 32 and 36 via the first control circuit 11. In this case, the reception is performed by the demodulation circuit 31.degree. synchronous/asynchronous conversion circuit 32. Transmission is performed via the asynchronous communication interface circuit 33. Synchronous/asynchronous conversion circuit 36. This is done via the modulation circuit 36.

As described above, according to this embodiment, by referring not only to the data value but also to the presence or absence of a framing error to determine the line protocol, the determination of asynchronous data transmission and synchronous data transmission can be made more accurately. It can be made to have a high value.

Effects of the Invention As described above, according to the present invention, a control circuit for controlling a switching device and a control circuit for controlling a synchronous/asynchronous conversion circuit are provided, respectively, and the conversion of the synchronous/asynchronous conversion circuit for reception is performed when determining the line protocol. By stopping the operation and supplying the demodulated data as it is to the interface circuit through the switch, it is possible to more accurately discriminate between asynchronous data transmission and synchronous data transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a line protocol discrimination device according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a block diagram of a conventional line protocol discrimination device. FIG. 4 is a waveform diagram for explaining the operation of FIG. 3. 11...First control circuit, 12...Second control circuit, 33...Asynchronous communication interface circuit, 34...Synchronous communication interface Circuit, 37...Switcher, 32...
- Reception synchronous/asynchronous conversion circuit, 36... Transmission synchronous/asynchronous conversion circuit, 31... Demodulation circuit,
36...Modulation circuit, 39...Microcomputer. Name of agent: Patent attorney Toshio Nakao and one other person φ

Claims (1)

[Claims] an asynchronous communication interface circuit, a synchronous communication interface circuit, a switch for switching which of the two interface circuits to use, a first control circuit for controlling the switch, and an output of the demodulation circuit. A receiving synchronous/asynchronous conversion circuit that converts synchronous demodulated data into asynchronous data when the other station performs asynchronous data transmission as input, and switching between the conversion operation and stop of the conversion operation of the reception synchronous/asynchronous conversion circuit. and a second control circuit that controls the output of the demodulation circuit by stopping the conversion operation of the reception synchronous/asynchronous conversion circuit when it is unclear whether the data transmission is asynchronous data transmission or synchronous data transmission. A line protocol discrimination device characterized in that it is configured to supply demodulated data as it is to the asynchronous interface circuit through a switch.