JPS6286582A - Pcm recording and reproducing device - Google Patents

Abstract

PURPOSE:To simplify hardware and to lower a master clock frequency by determining the number of samples in one frame and the number of frame bits based on a prescribed relation to make the number of the frame bits equal to the number of quantizing bits more than two. CONSTITUTION:When the PCM data of an N channel is distributed into Tr tracks to record and reproduce, the number of bits TA of one frame is considered to be TA = n X (least common multiple of the number Bi of k quantizing bits) + m and TA and TB = N X (the number S of samples of one frame) XTr constitute a simple integer ratio. In the expression, n is an integer and m is the number of additional bits such as a synchronous signal. For the number of the quantizing bits >=2, the number of the frame bits can be made equal, a hardware is simplified and a master clock frequency is lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PCM recording and reproducing apparatus that provides an optimal number of bits for a frame configuration for a plurality of types of quantization bit numbers.

[Conventional technology]

The analog signal is sampled at the sampling frequency Fs, and A/
Perform D conversion and convert to PCM data, and convert several sleeves of PCM
There is a PCM recorder as a device that collects data into a frame structure, distributes it to multiple tracks, and performs MC recording and playback. These PCM The recording device frames/
There was something shown in the 8th bad as Block M&. (a) is a frame configuration, and (b) is a t-niblock configuration. One frame consists of 252 bits, 12 samples of PCM data with 16 quantized bits, 10 bits of synchronization signal, 2 bits of control signal, and 16 bits of 01 check data for error detection and correction. (
b) is a block configuration, and the frame configured signal is
6 tracks for M data, 2 for error detection and correction
Record on a total of 8 tracks. The third frame structure is determined as follows. Now, let the number of channels of the analog signal be S, and the number of samples constituting one frame be S.
When the number of tracks on which PCM data is recorded is Tr, the frame and block frequencies FB are given by the following equations.

5XN FB = □ ... (3) XTr If the number of bits in one frame is Ts, then Ts = BX
S+m-(4).

Here, B is the number of quantization bits of one sample, and m is the number of additional bits such as a synchronization signal. The number of transmission cycles Fc of bits in a frame is Fc=FaXTs...(
5) is given by At this time, if FC and FsXN are a simple integer ratio, then Fc and FsXN can be obtained from one clock.
Therefore, S and m are selected so as to make this possible. In the case of FIG. 8, N=2. S=14. Tr=
6, the block frequency FB is Fs = 4
If there are 8 fish, FB = -1 color -1-! −= 1.14
It is 8 kHz. Since the synchronization 4 x 6 signal is 10 bits, the control signal is 2 bits, and the CI inspection data is 16 bits, m = 10 + 2 + 16.
= 28° Also, since B = 16, from equation (4), '
I'5=16×14+28=252 bits. Therefore, from equation (5), F c =252 xl, 148k) h
= 288kHz, and the ratio of Fc and FcXN is 288
:48X2=8:1, which is a simple integer ratio. Such a lock can be generated by a fourth worst clock generation circuit. In the figure, (1) is the master clock oscillator, (2) is the 6 frequency divider, (3) is the 42 frequency divider, and (4) is the frequency divider.
) is a 252 counter, (5) (6) (force (8) is the output terminal. Master clock oscillator (2881 at υ)
is generated and sent to the divide-by-6 circuit (2), 252 counter (4), and output terminal (6). The output of the divide-by-6 circuit (2) is 48 klb, and the output of the divide-by-6 circuit (3) and the output terminal (
8). The 252 counter (4) outputs a lock signal to the output terminal (5), which is necessary for generating synchronization signals, control signals, etc. The block frequency FB is outputted from the (transfer) splitter to the output terminal (8).

The block failure of the PCM recording/reproducing apparatus having such a frame structure is shown in the sixth failure. In the figure, (9) is a 2-channel analog signal input terminal, QQ is an A/D conversion circuit, Uυ is an encoding circuit, (6) is a track distribution circuit, α2 (io4Jtea is a modulation circuit, 4 (7) Clυ is a recording amplifier, 4 (7) Clυ is a recording head, Cl4W- is a playback head, spider VO is a playback amplifier, spider (4) ■ is a demodulation circuit, and the left end is a time base correction circuit (hereinafter referred to as TBC circuit). omitted),
咉 is a decoding circuit, flash is a digital-to-analog conversion circuit, 圓 is a channel analog output terminal, and (9) is a clock generation circuit. Next, the operation will be explained. First, on the recording side, the analog signal input from the input terminal (9) is
D conversion conversion circuit Converts to PCM data with quantization bit number B = 16 dn1 encoding circuit (b) Two types of error correction detection codes for C2 test data and CI test data so that errors caused by media such as tape can be corrected and detected or added. A control signal is added to the encoded signal by track distribution circuit 4, and the signal is distributed to 8 tracks and sent to modulation circuit α3ti.
41 (Send to LF9. Modulation circuit 0314111f
After being modulated into a signal suitable for recording and reproducing on a 1F medium, a synchronizing signal is added, and the signal is recorded on the medium from the recording amplifier 40η (g) to the recording head 4 (7) 2υ. . On the playback side, the signal played by the playback head Sohan■ is amplified by the playback amplifier c#C# (B), the demodulation circuit @ Yotsuyama detects and protects the synchronization signal, performs clock playback, and reproduces the clock. TBC circuit G3J)
Send to www. The TBC circuit circuit 8 removes the moxibustion device, etc., and sends it to the decoding circuit. The decoding circuit performs error correction and detection using the C1 test data and C2 test data, and the D/Ag conversion circuit converts the signal into the original analog signal, which is output from the n output terminal (7). Note that the control signal is used to control the device, such as the presence or absence of Fs type emphasis. The clock generation circuit is mainly constructed based on Fig. 4, and Fs is A.
/ D converter quantity, D/A converter -, F c * FB
The output of output terminal (5) is sent to track distribution circuit 4 and modulation circuit α3σ4 (lf9.TBc circuit c+l1w cw).

The conventional frame configuration is as shown above, so
In order to accommodate the second quantization bit number B, = 20, the frame/block configuration shown in FIG. 6 can be considered. From Figure 8, only the number of quantization bits is changed, so from formula (4), Ts = 20 x 14 + 28 = 308
, from formula (5), Fc = 1.148k)h x 808
=852k)h.

In this way, the number of bits in one frame is the number of quantization bits 1
6 is 252. The length is different from the number of i quantization bits, 808. The main part of the clock generation circuit corresponding to these two quantization bit numbers is shown in FIG. In the figure, □□□ is an 8.168 M master clock oscillator, ■ is an 11 frequency divider, the ring is a 66 frequency divider, 1υ is a 9 frequency divider, (6) is a 252 counter, and the ring is a 42 frequency divider. , - is 8
08 counter, -1471-4 stages are output terminals.

When the number of quantization bits is 16, a 4θ signal is used at the output terminal, and when the number of quantization bits is 20, the configuration is as shown on the output, so there are the following drawbacks. Masu, 4th
As you can see from the 7th cause, the frequency of the master clock is 11 times higher, from 288k)h to 8.168M, and PCM recording and reproducing equipment uses various clocks for encoding etc. The disadvantage is that the degree of freedom is reduced and it is difficult to use. Next, the output terminal-ring signal is sent to the track distribution circuit U1TBC circuit 6υ) to the moxibustion,
Since these circuits usually use memory, they have the disadvantage that their control becomes complicated if the number of bits in one frame differs. Furthermore, if the number of bits in one frame is different, the synchronization signal protection circuit in the demodulator circuit m-m will not work, and the clock sent to the TBC circuit cIη must be switched for each track, making the hardware complicated. There were drawbacks such as.

This invention was made to solve the above-mentioned problems, and the master clock does not increase even if the number of frame bits is the same for two or more quantization bit numbers, and the number of track distribution circuits and modulation circuits increases. The object of the present invention is to obtain a PCM recording and reproducing device in which a3 (141 us), a demodulation circuit (up to) four peaks, and a TCB circuit (6υ up and down) can be easily configured.

[Means for solving problems]

The PCM recording and reproducing device related to this occurrence uses equations (1) and (2) to calculate the number of samples S in one frame, frame bits, and so on so that the number of frame bits is the same for two or more quantization bit numbers. The number TA is determined and recorded and reproduced.

[Effect]

The frame structure in this invention is such that one frame is composed of an integral multiple of the least common multiple of two or more quantization bit numbers and additional bits such as a synchronization signal, and the number of channels N, the number of samples in one frame S, and the number of tracks. The product of Tr and the number of bits in one frame are determined to be a simple integer ratio.

[Embodiments of the invention]

An embodiment of the present invention will be described below. 1st
(a) is the frame configuration, (b) is the block configuration, and includes a 16-bit synchronization signal, 8-bit control signal, 820 PCM data or test data, and C1.
The test data is 16 bits, a total of 860 bits. This frame configuration is determined as follows. Number of channels N=2. PCM data distribution track number Tr = 6
．． 2 Number of quantization bits for type m, B, = 16, B, =
20, LCM (Br, B2
) = 80. 80 bits/16 bits: 6, but in the case of 2 channels an even number is desirable, so 80
Table 19 Table 2 is the result of calculating the formula (υ(2)) assuming that 2 = 160 bits and collecting the simple ratios of TA and TB.Table 1 shows the case where the number of quantization bits B is 16 bits. , Table 2 is for the case where the number of quantization bits B2=20.

Table I When B1=16 bits 2
When B2=20 bits, P:Q represents the ratio of TA and TB, and here, the ratio of Q to 10 or less is mentioned. Also, FM is the master clock frequency. Since m includes a synchronization signal, a control signal, and C1 test data, an even number between 24 and 48 bits is shown. Table 19 In Table 2, those with TA of the same number of bits are selected, and the one with TA = 360 bits is the first worst frame/block configuration.

The main part of the clock generation circuit that realizes this frame/block configuration can be realized by the second method.

In the second case, (5υ is the master clock oscillator, Q
is a divider of 5, 0 is a divider of 80, - is a divider of 4, and phosphorus is a divider of 60.
Frequency divider, bag is 48 frequency divider, 67) is switch, - is 860
The counter, wmeutetn-, is an output terminal.

As is clear from Table 11 and Table 2, the master clock oscillator train generates 1.44 M, which is sent to the 5 frequency divider circuit (2), the 80 frequency divider circuit (1), and the 4 frequency divider circuit (2). The output of the 5 frequency divider circuit is the bit frequency F corresponding to the quantization bit number B, = 16.
c1 = 288k)h and is sent to output terminal 6. The output of the 4 frequency divider circuit becomes a bit frequency Fc2=860 kHz corresponding to the quantization bit number B=20, and is sent to the output terminal. The output of 80 divider Q is Fs
= 48 kFk, 60 frequency divider circuit - 148 frequency divider circuit -
1 is sent to output terminal tSU. 60 frequency divider circuit - 148 frequency divider circuit - output FB1 = 0.8kHz, FB2 = 1k)
lZ is sent to output terminals ① and 4, respectively. The switch @ selects and switches the output of the 5 frequency divider when the quantization bit number B = 16 to the output of the 4 frequency divider when the quantization bit number B = 20.

Note that in the above embodiment, the number of channels N=2. Although the case where the number of tracks Tr = 6 has been described, it is clear that the number of frame bits can be determined from equation (1) (21) even with other numbers of channels and tracks. Also, in the above embodiment, the number of quantization bits is In the case of type R=2 (B1=
16. B2=20), but it goes without saying that equations (1) and (2) are also valid for n or more.

Further, in the above embodiment, an example of a multi-track recording/reproducing apparatus with Tr=6 was shown, but one transmission line can record track 1. Track 2. ..., track 6, track 7, track 8. It is also applicable when recording and reproducing sequentially such as tract...

〔Effect of the invention〕

As described above, according to the present invention, since the number of frame bits can be made the same for two or more quantization bit numbers, the hardware of the recording/reproducing device can be simplified and the frequency of the YASTER clock can be lowered. There is.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a frame/block configuration according to an embodiment of the present invention, Fig. 2 is a block diagram of a clock generation circuit according to an embodiment of the invention, and Fig. 8 is a diagram showing a conventional quantization bit number. 16, the fourth figure is a block diagram of a conventional clock generation circuit, and the fifth figure is a block diagram of a conventional clock generation circuit.
The figure is a block diagram of a multi-track PCM recording and reproducing device. The sixth figure shows the frame/block configuration when the number of conventional quantization bits is 20. The seventh figure shows the frame/block configuration in the case of a conventional quantization bit number of 20. FIG. 2 is a block diagram of a clock generation circuit for realizing the configuration. (5υ is the master clock oscillator, C54
is a 5 frequency divider, Sir is an 80 frequency divider, Akane is a 4 frequency divider, and So is a 60 frequency divider.
Frequency divider, fit 48 frequency divider, Φη is switch, world is 86
It is a 0 counter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (3)

[Claims] (1) Analog-to-digital conversion (hereinafter referred to as A/D) of N-channel (N: integer) analog signals at sampling frequency Fs
In a PCM recording and reproducing apparatus that performs conversion (abbreviated as "conversion") into PCM data, composes some PCM data into a frame structure, and distributes the PCM data to Tr (Tr: an integer) tracks for recording and reproduction. When the number of k quantization bits is Bi (i=1,...,k), the ratio of TA and TB given by the following formula is expressed as a simple integer ratio, and each number of quantization bits is PCM characterized in that the same TA is recorded as the number of bits of one frame in
Recording and playback equipment. TA=n×LCM(Bi(i=1,...k))+m・
...(1) TB=N×S×Tr...(2) Where, n: Integer m: Number of additional bits such as synchronization signals LCM(Bi(i=1,...,k): Bi( i=1,
..., k) least common multiple S: number of samples composing one frame (2) The PCM recording and reproducing apparatus according to claim 1, characterized in that k=2, B1=16, and B2=20. (3) N=2, Tr=6, k=2, B1=16, B2=
20, n=4, m=40 and the number of bits in one frame is 3
A PCM recording and reproducing apparatus according to claim 1, characterized in that the PCM recording and reproducing apparatus is 60 bits.