JPS628662A - Data restoring circuit - Google Patents

Abstract

PURPOSE:To restore and process a compressing data at high speed by providing a parallel shifter and processing to give and receive in parallel the data between the memory of the compressing data and a table for the restoration. CONSTITUTION:When an MH code compressed by a CPU 2 is written in a picture buffer 3, a scanning start synchronizing signal from the engine of a printer is inputted to an engine interface 10, the picture buffer 3 outputs the data to a shifter 5 by an address from an address counter 4. The shifter 5 shifts so that the head of the MH code decoded next comes to the higher order bit of 16 bits of CODE 15-0 to be outputted and the MH code is restored with the run length as the binary data of 12 bits by a decoding table 6. An output control part 9 fetches the serial data from a run length counter 7 into a latch circuit 9a and sends the data of 8 bits of the parallel to an interface 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data restoration circuit for restoring compressed image data in an electrophotographic printer such as a laser printer or an LED printer.

[Prior art and its problems] In general, when using a laser printer as an output device, there are two ways to transfer data sent from a host computer device such as a word processor: one is to send code information such as a character code, and the other is to send images as dot data. There are cases where it is sent: There are two types of code information: the bitmap method and the character map method. Of these, the bitmap method can print arbitrary characters in any position and has functions such as full graphics, but Since the operation of the printer cannot be stopped midway, the memory is expensive because it requires a capacity to store at least one page's worth of data. Furthermore, in the dot data transfer method, if the transfer speed from the computer device is controlled to perfectly match the print dot data output speed of the printer, the data from the computer device is output as is as print data. However, because the processing speed of a computer device is generally slower than that of a printer, and the data transfer cannot be synchronized, it is possible to print on the printer side regardless of the data transfer speed of the computer device. There is a need to. However, even in this case, electrophotographic printers have a fixed process speed depending on the sensitivity of the photoreceptor and the characteristics of development, transfer, etc. For example, like thermal printers, the paper feed speed can be varied and the process speed can be changed to a computer device. Since it is not possible to use a method that matches the timing of data transfer, it is necessary to provide a buffer memory on the printer side to store about one page worth of dot data sent from the computer device, which also requires a large capacity memory. required and became expensive.

Therefore, the memory capacity can be reduced by compressing the data by encoding the data sent from the computer device and then storing it in the memory. In this case, the compressed code is It is necessary to restore the original signal.

The restoration method is described in Japanese Unexamined Patent Publication No. 58-170280, and will be briefly explained below using the block diagram of FIG. 8.

Raster data from a computer device or the like is compressed by a CPU (central processing unit) 21 and written into a memory 22. After the data written in the memory 22 is taken in by the shifter 23, the compressed data is decompressed by the decoder 24 and output to the engine 25 of the printer driving section.

Serial data from the memory 22 is input to this shifter 23, and data is taken in one bit at a time by a shift signal from a decoder 24.

Therefore, if the data output from the memory 22 has n pits, it needs to be shifted once, and n clock pulses are required to capture one piece of data, which increases the processing time and increases the processing time of the printer. The disadvantage was that the image signal could not be output in synchronization with the system speed.

[Object of the Invention] The present invention has been made in order to eliminate the above-mentioned problems, and an object thereof is to provide a data restoration circuit that can restore compressed data at high speed.

[Structure of the Invention] The data restoration circuit of the present invention includes a memory that encodes and stores the run length of image data, and a data that is outputted from this memory with a predetermined number of bits and is then restored by appropriately shifting the data. A shifter circuit outputs the run length code so that it becomes the beginning of data, and a restoration memory restores the run length code output from the shifter circuit and outputs the run length in binary code. The data restoration circuit is characterized in that a parallel shifter is used as the shifter.

[Summary of the Invention] FIG. 1 schematically shows a block diagram of a plink using the data recovery circuit of the present invention. The shifter 26 takes in predetermined bits of parallel data output from the memory 22 that encodes and stores the run length of image data, and shifts it as appropriate so that the run length code to be restored next becomes the beginning of the data. ing.

As a result, the data output from the memory 22 can be taken into the shifter 26 by one software operation, and the data can be restored at high speed.

[Embodiment] First, data compression and restoration necessary for this invention will be explained. The compression uses the Modified Huffman (Ml() method, which is a modification of the Huffman code that theoretically provides the highest compression rate, and the run length is a long series of white or black dots as shown in the following table). The dots are encoded separately.

Modified Huffman code table run length White run Black run 1 (100+11 0104 to
ll 011128 1001F
0000110010001728 0100
+1011 0000001100101EOL
000000000001 00000000
0001 This compression process is performed using a compression conversion table in the CPU, and the CPU2+ detects the change point from the white run to the black run while importing the raster data sent from the outside, and calculates the number of dots up to the change point. The MH code with the corresponding white run length is searched from the compression conversion table, written to the memory 22, and then the data is imported.This time, the change point from black run to white run is detected, and the black dots up to this change point are The MH code of the black run length corresponding to the number is similarly searched and written into the memory 22. Each line sent as raster data is arranged so that it always starts with a white run, and if it starts with a black run, it is set to "0".
A long white run is inserted.

Therefore, the MH code and the code length of the MH code are stored in this compression conversion table so that the compression conversion is performed in accordance with the input raster data.

Incidentally, the code lengths to be converted are 4 bits to 9 bits for white runs, 2 bits to 13 bits for black runs, and 11 bits to 12 bits for black and white common runs. Therefore, as shown in Figure 2, the data for one run length has a 2-byte structure consisting of 16 bits stored in two addresses, and the code length of the MH code is in binary in the upper 4 bits of the first address. -, and the Mll code is stored in left-aligned 12 bits. However, in the case of a black run with a length of 13 hits, the high-order 1 bit, 0, is omitted and stored as 12 bits. With this configuration, codes up to 4 bits in length, which are frequently converted, can be compressed and converted by accessing 1 byte. The data in the bit array encoded in this way is stored in memory 2.
It is written to address 2 in units of 8 bits, which is 1 byte.

In this case, as shown in FIG. 3, byte boundaries are ignored, bits are compressed, and the data is written as a linear address. still,
If all lines in one scan are white dots, the white run length for one line is not compressed and encoded, but simply EO
Make sure to include only the L (end of line) code,
Also, if there are only white dots in the effective image area in one scanning line, an EOL code is also inserted.

Further, the decoder uses a restoring table memory, such as a ROM, for restoring data, and stores the content of data written in the memory in accordance with the MH code as an address in the ROM. Data based on this MH code has a maximum length of 13 bits, and when stored, the most significant bit of the data must be used for switching between the white run table and black run table, and the stored data is 14 hits. . Therefore, the restoring table ROM uses 14 lines as address lines. As shown in Figure 4, the data to be output from this restoration table is 12 bits of binary data necessary to represent a run length of up to 2560 and 4 bits of binary data necessary to represent a code length of up to 13 bits. There are a total of 16 bits, and two restoration table ROMs are used so that this 2-byte signal can be output.

FIG. 5 shows one embodiment of the invention. The configuration and operation will be explained below.

The external interface l is a part connected to a raster data output type computer device, and specifically, a parallel interface such as Centronics or R9232.
C, r (serial interface such as S422).

CPU2 includes a microprocessor, program memory,
It consists of a system RAM memory and a table memory for compressing and converting the raster data from the bipedal interface 1 into MH code by software, and the MI-1 encoded data is stored in the image buffer according to the predetermined procedure as described above. Be written in 3. Image buffer 3 is RAM
It consists of a memory consisting of 16 when writing.
It is connected to the CPU 1 by an address bus for focus Δ0 to 15 and a data bus for 8 bits DO to 7, and one page worth of data from the CPUI is written to the memory. During printing, the image buffer 3 is separated from the CPU Address counter 4 is set by MAO-16 address bus.
and the 16-bit 13FOUTO~1
It is connected to the shifter 5 by a data bus 5. The address counter 4 is connected to the image buffer 3 via the address bus.
This circuit generates an address for reading out the memory in the image buffer 3, and the generated address is held in the latch circuit h of the image buffer 3. Data at a predetermined address is read by this access of the address counter 4, and is sent to the shifter 5 in units of 16 bits via the data bus. The shifter 5 takes input 16-bit data into a latch circuit 5a within the shifter 5, and outputs signals C0DEO to 3 from a decoding table 6, which will be described later.
The signals are shifted by the number indicated by and output as signals C0DE15-0.

FIG. 6 shows a circuit diagram of the shifter 5. two 16s
Bit latch circuit 1.2 and 16 input terminals DO~
It consists of 16 selectors 0 to 15 that select and output only one from DI5.

The output terminal of latch circuit 2 is connected to the input terminal of latch circuit 1, and 16 consecutive sets of 16 output terminals are taken out from the 32 output terminals of latch circuits 1 and 2 by shifting one terminal at a time. Each output terminal taken out is connected to the input terminal of selectors 0 to 15, respectively. Signals C0DEO to 3 indicating the shift amount are input in binary form to the selection terminals A, B, C, and D of each selector 0 to ■5, respectively, and the signal C0DEO to 3 indicating the shift amount is inputted from each output terminal YO to Y15.
It is output as DEO~15. The control line 7 PEI is connected to the latch circuit 1.2, and the PI
When PEI falls for the first time, first code data BFOUTo~15 from the image buffer 3 is taken into the latch circuit 2 and output as signals Sr3.16~SB31. At this time, the input terminal of the launch circuit 2 has a second
When the second falling edge occurs, the second code data is sent to the latch circuit 2 from 5BI6 to S.
The first code data is output as SBO-5B15 to the output terminal of the latch circuit 1.

In this way, the output terminals of latch circuit 1.2 are connected to SBO to S.
The first code data consisting of 32 bits of B31 and the second
code data is output at the same time. Selection terminal A, B
, C, D are input with signals C0DEO~3 that do not indicate the shift amount. For example, when "3" is input as the shift amount, the input signal SB of the input terminal D3 of each selector 15~0 is input.
3. SB4゜...Si217. S[318 are output to output terminals Yr5 to YO, respectively. Therefore, 16-bit signals SB3 to SB+8, which are softened by 3 bits from the beginning of 32 bits SBO to SB31, are output.

The following table is a decoding table for selecting input terminal Do-D+5 for 4-bit binary numbers input to selection terminals A, B, C, and D.

In this circuit diagram, two 16-bit latch circuits are used to create a 32-bit configuration, or one 32-bit latch circuit may be used.

The decode table 6 is the Ml output from the shifter 5.
This is a restoring circuit for restoring the signal C0DE 15~0 based on the l code, and using the restoring table flOM in the decoding table 6, the run length is RLJ N O~
1j1 with the binary data of 11, and the coat length of this input Ml-1 code as COD E O~
3 binary data is sent to the notation shifter 5. Therefore, the data in the shifter 5 is output after being knotted by the number of bits equal to the M I code length decoded by the decoding table 6, so the upper bits of the signals C0DE15 to 0 must be input to the decoding table 6. C0DE of
The beginning of the MH code to be decoded next is located at I5.

The run length counter 7 outputs the binary run length data inputted from the decode table 6 as a serial black or white signal BLK/Wl(T), and also outputs the binary run length data inputted from the decoding table 6 as a serial black or white signal BLK/Wl(T). /W II
The 'I' signal is inverted, and data from the decode table 6 is latched into the latch circuit 7a of the run length counter 7.

When the EOL code is output from the shifter 5, the EOL detection circuit 8 detects this and controls the control line EOL to signal all of the - rows as white.

The output control unit 9 converts the serial data from the run length counter 7 or the EOL signal from the EOL detection circuit 8 into a predetermined 8-bit parallel signal LDDATAO~7, and then outputs the signal to an engine interface lO connected to the engine of the printer. It is being sent to The pipe signal generation circuit 12 is a circuit that generates signals to control each of the blocks described above, and is a circuit that generates signals for controlling each of the blocks described above. The control line INPR is connected from the run length counter 7, output control unit 9 and engine interface IO.
Control the ding.

Next, the operation of the block diagram of the above configuration will be explained with reference to the time chart of FIG.

When the control line [NPRNT from the CPU 2 becomes “■]”, that is, becomes non-active, the image buffer 3
2, and the MH codes compressed by the CPUI are written into the image buffer 3 one after another.

In this CPU mode, the pipe signal generation circuit 12
゜Address counter 4. Shifter 5. Run length counter 7
And the output control section 9 is in the initial state. When one page of data is written to the image buffer 3, the CPU 2
When the engine interface 10 is activated via the control line and further made T'PRN T = L, that is, active, the image buffer 3 is disconnected from the CPU 2 and connected to the address counter 4 and shifter 5, and Each block after the image buffer 3 becomes operational and enters print mode.

Next, when a one-line scan start synchronization signal from the external engine is input to the engine interface IO, the control line RYOYADI falls in a pulsed manner.

As a result, the control line ENP lPE from the output control unit 9
2 becomes "L", that is, active, and pulses that fall at constant time intervals are generated on the control lines PIPEI and PIPE2 from the pipe signal generating circuit 12. Also, the control line ENPIPEI from the run length counter 7 is the control line PIPEI.
This is a control line to enable only the P.I.P.
EI is the address counter 41 image buffer 3. Shifter 5. P['E2 is connected to the decode table 6 and run length counter 7, and P['E2 is connected to the run length counter 7 and output control section 9, and each block has PIPEl, PI
The processing assigned to each block is completed within the interval between pulses generated in PE2.

In this print mode, the address counter 4 is
Every time IPEI falls, the counted address is MA
The 17 bits from O to 16 are sequentially sent to the image buffer 3, the address of the image buffer 3 is accessed, the data written in the memory is read, and the shifter 5 is sent to the BF.
Output as 16 bits from OUTO to I5. Note that when the control line C0UNTEN from the shifter 5 is "H", the counted address is not sent out from the address counter 4 even if PIPEI falls.

In shifter 5. As described above, the input data is taken in and shifted so that the top of the next MH code to be decoded is placed in the upper bits of the 16 bits of output C0DE 15 to 0, and then sent to the decoding table 6. In decode table 6, the MII code has a run length of RUNL.
It is restored as 12-bit binary data of 0 to 11 and sent to the run length counter 7. This run length counter 7 serially outputs data indicating the length of white or black, and each time it outputs white or black serial data,
The signal BLK/WHT indicating white or black is inverted. When the control line "1" falls, BLK/WHT is set to i to I level. Next, when the PIPEI falls, the input run length value is preset in the run length counter. This preset BLK/WHT when the value is O
is inverted, and when it is I, BL is applied at the falling edge of PIPE2.
K/WHT is inverted. When this preset value is 2 or more, ENPIPE1 is deactivated and PIPE
The falling of I is prohibited and the operation up to the run length counter section is stopped. Then, the preset value is subtracted every time PIPE2 falls, and when this preset value becomes 1, BLK/WH〒 is inverted, and ENP I PEI
is being returned to active. The output control unit 9 controls yσ
It has a counter that is set to “8” at the falling edge of the signal.
At each falling edge of V, the serial data from the run length counter 7 is taken into the latch circuit 9a in the output control section 9, and the set value is counted up to 1.
It is reduced by increments. When this count value becomes 0, the count value is set to 8 again and ENP I PE2
becomes inactive, and PIPEI and PIPPE2
falling is prohibited, and each block 3, 4, 5, 6, 7
．． The operation at 9 stops. At this time, 8-bit data is latched in the latch circuit 9a, and when the control line LDREQ from the engine interface IO falls in a pulsed manner, the data is sent from the output control section 9 to the engine as parallel 8-bit LDDATAO~7. is sent to the engine via the interface 10, and at this time the EN
r'1PE2 returns to active. When the EOL signal is input to the output control unit 9, ENPrPE2 becomes non-active unconditionally, and in this case, ENPrPE2 returns to active at the next fall of σ.
After the signal is generated, the signal from the run length counter 7 is invalidated from the rising edge of LDREQ until the falling edge of LDREQ.

As explained above, in this embodiment, signal processing is not performed step by step in each block, but by controlling each block with a clock pulse from the same pipe signal, the signal processing assigned to each block is are performed in parallel within the pulse interval of the clock. That is, the address generated by the address counter 4 changes from a-+b→C+d→e by the pulse from the control line PIPEl.
→ r, the image buffer 3 takes in the address of e at time L1 when the address of f is generated, and prepares the data corresponding to the address of e as output by time t when the next pulse is generated. do. Shifter 5 is at time t
1, the output BFOUTO~15 of the image buffer 3 generated by the address d is taken in, and RLINO~11 corresponding to the address d is prepared as an output by time t2. The run length counter 7 takes in RUNLO~11 generated from the decode table 6 at the address of C at time t1, and the output control section 9 takes in the BLK/WH generated by the run length counter 7 according to the address of b. .

In this way, each block processes different data within the same timing, so signals can be processed at high speed in the above block diagram.

Furthermore, since the shifter 5 is a parallel shifter, a maximum of 16 bits of data can be shifted in one shift operation, and the compressed data can be restored at high speed. Although the above embodiment has been described with respect to a printer using an electrophotographic method as an image forming apparatus, the present invention is generally applicable to an image forming apparatus in which the speed in the sub-scanning direction cannot be changed, such as a CRT display apparatus.

[Effects of the Invention] The data restoration circuit according to the present invention includes a parallel shifter for receiving parallel signals between a memory storing compressed data of image data and a restoration table for restoring the compressed data, and Since the transfer of data between the memory and the restoration table is processed in parallel, predetermined compressed data from the memory can be input to the parallel shifter and processed in one shift operation, for example. Compressed data can be restored at high speed in an interface for transferring image data to a printer.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an overview of a printer to which this invention is applied, Fig. 2 is a bit arrangement diagram of conversion data stored in a compression conversion table, and Fig. 3 is an arrangement of MH codes written in memory. Figure 4 shows the restoration table RO.
FIG. 5 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a wiring diagram of the shifter in Figure 5, Figure 7 is a time chart showing the operation in the block diagram of Figure 5, and Figure 8 is a wiring diagram of the shifter in Figure 5.
The figure is a block diagram showing a conventional restoration method. l...External interface, 2...CPU. 3... Image buffer, 4... Address counter,
5... Shifter, 6... Decode table, 7
...Run length counter, 8...EOL detection circuit, 9
...output control unit, lO...engine interface,
11...Dynamic ram control unit, 12...Pipe signal generation circuit.

Claims (3)

[Claims] (1) A memory that encodes and stores the run length of image data, and by appropriately shifting the data output from this memory with a predetermined number of bits, the run length code to be restored next becomes the beginning of the data. A data restoration circuit comprising a shifter circuit that outputs the data as described above, and a restoration memory that restores the run length code outputted from the shifter circuit and outputs the run length as a binary code, A data restoration circuit characterized by using a shifter. (2) The above shifter has 2n bits BI_1 to BI_2
A latch circuit that takes n as an input and outputs 2n bits BO_1 to BO_2n, and an input terminal So-S that takes n bits as an input and selects only one bit from among these n bits.
The first selector receives n bits of BO_1 to BOn, and the second selector receives n bits of BO_2 to BOn_.
+_1 is input, and like this 2n bits of BO_1~
2. The data restoration circuit according to claim 1, wherein the connection is such that consecutive n bits from BO_2n are sequentially input with a shift of 1 bit, and the selection input terminals of each selector are connected to each other. (3) The latch circuit of the shifter consists of two n-bit latch circuits, the output of the first latch circuit is used as the input of the second latch circuit, and the n-bit output of the first latch circuit is used as the input of the second latch circuit. The n-bit output of the second latch circuit is configured to provide a 2n-bit output, and the n-bit BI_1 to BIn is input to the first latch circuit, and BI_1 to BIn are latched at the first latch timing.し、BO_1〜BO
BIn_+_1 to BI_2n which is output as n and appears at the input of the first latch circuit at the second latch timing.
is latched and outputted as BOn_+_1 to BO_2n, and at the same time, at the first latch timing, the output data BO_1 to BOn latched by the first latch circuit is latched and outputted as 2n bits of BO_1 to BO_2n. The data restoration circuit according to item 2.