JPH0419836U

JPH0419836U -

Info

Publication number: JPH0419836U
Application number: JP1990057099U
Authority: JP
Priority date: 1990-05-30
Filing date: 1990-05-30
Publication date: 1992-02-19

Description

[Brief explanation of the drawing]

第１図はこの考案の実施例を示すブロツク図、
第２図はその変形例の一部を示すブロツク図、第
３図は従来のクロツク発生回路を示すブロツク図
である。 Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a block diagram showing a part of a modification thereof, and FIG. 3 is a block diagram showing a conventional clock generation circuit.

Claims

[Claims for Utility Model Registration] Multiply the frequency of a reference signal by N/M using a variable frequency circuit (N and M are positive integers), input the output of the variable frequency circuit to a phase-locked loop as a reference, and achieve the desired purpose. A digital value corresponding to the amount of delay is converted into an analog signal by a DA converter, and the analog signal is supplied to the phase-locked loop, and the output of the variable frequency circuit is used as a reference, and only the amount corresponding to the digital value is generated. In a clock generation circuit that outputs a delayed clock, an analog converter generates an analog signal corresponding to the N/M, and the output of the analog converter is supplied to the DA converter as its conversion reference signal. Characteristic clock generation circuit.