JPS6286818A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable metal of a high melting point to be buried into a contact hole, by forming polycrystal silicon-layered sidewalls on side faces of an insulating layer inside the contact hole by an anisotropic etching method and making a metal of a high melting point selectively grow inside the contact hole. CONSTITUTION:An insulating layer 2 is attached to a base 1, and an opening of a contact hole 3 is made in the insulating layer 2. A polycrystal silicon layer 4 is attached to cover the contact hole 3 and then sidewalls 4A are formed of silicon layers 4 on side faces of the insulating layer 2 inside the contact hole 3 by anisotropic etching method which prevails vertically. Metal 5 of the high melting point is made to selectively grow inside the contact hole 3. Hence, the metal 5 of the high melting point can be buried into the contact hole 3.

Description

[Detailed Description of the Invention] [Summary] By forming a sidewall of polycrystalline silicon (polySt) in the contact hole, the inside of the contact hole can be completely filled and flattened during the subsequent selective growth of a high melting point metal. Do it like this.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of flattening a contact hole to form a contact between a base and a conductive layer.

As devices become more highly integrated and multi-layered, local steps become thicker (for example, the bit lines of highly integrated DRAMs (dynamic random access memories) [aluminum
AI) The contact hole formed by the wiring pattern is
The diameter of the contact hole is about 11) m, and the depth is about 1.5 μm, and the problem of covering the step of the At layer in the contact hole is becoming serious.

Therefore, it is important to flatten the substrate in order to prevent problems such as disconnection of the wiring pattern due to the step and to improve the precision of the next process.

C. Prior Art] FIG. 2 is a cross-sectional view illustrating a planarization process of embedding a high melting point metal into a contact hole according to a conventional example.

In the figure, reference numeral 1 denotes a semiconductor substrate, which is a silicon (Si) substrate, and an insulating layer made of silicon dioxide (Si) with a thickness of 1 μm.
O□) layer 2 is deposited and contact holes 3 are opened by conventional photolithography.

Next, a high melting point metal such as tungsten (W) is selectively grown only on the Si by chemical vapor deposition (CVD) to fill the inside of the contact hole 3. 21 is a single layer grown selectively.

In this case, the selective growth of the layer 21 is only possible to a thickness of about 5,000 layers, and if the growth continues beyond that, the selectivity will be lost and it will also grow on 5iO2JiiZ.

Therefore, it is insufficient for flattening contact holes in highly integrated devices.

Han's CVD conditions use tungsten hexafluoride (WFs), hydrogen (H2), and oxygen (0□) as reaction gases, reduce the pressure to Q, about 5 Torr, and perform thermal decomposition at 320°C.

[Problem that the invention seeks to solve]

Conventional selective growth of high melting point metals cannot sufficiently fill contact holes, and therefore it is difficult to planarize the substrate.

[Means for solving problems]

The solution to the above problem is to make the base, for example, a silicon (Si) substrate (
1) An insulating layer (2) is deposited on top, a contact hole (3) is opened in the insulating layer (2), and a polycrystalline silicon layer (4) is deposited to cover the contact hole (3). , a side wall (4) made of the polycrystalline silicon layer (4) is formed on the side surface of the insulating layer (2) in the contact hole (3) by anisotropic etching that is predominant in the vertical direction.
This is achieved by the method for manufacturing a semiconductor device according to the present invention, which includes the steps of forming a contact hole (A) and selectively growing a high melting point metal in the contact hole (3).

[Effect]

In the present invention, by depositing a poly-Si layer on the side surfaces of the contact hole, subsequent metal growth can be performed from the side surfaces as well, thereby completely filling the contact hole.

〔Example〕

FIGS. 1(1) to 1(3) are cross-sectional views illustrating a planarization process of embedding a high melting point metal into a contact hole according to the present invention.

In FIG. 1(1), (1) uses a Sii plate as a base, on which a 1 μm thick Si layer 2 is deposited as an insulating layer, and a contact hole 3 is opened by ordinary photolithography.

Next, a poly-Si layer 4 having a thickness of approximately 500 nm is grown to cover the contact hole 3 using the CVD method.

The CVD conditions for poly-Si are monosilane (
Using Sit(a), the pressure is reduced to 0.2 Torr and thermal decomposition is carried out at 620°C.

In FIG. 1(2), anisotropic etching with a predominance in the vertical direction is performed by reactive ion etching (RIE) to form a side wall 4^ made of poly-Si on the side surface of the contact hole 3.

In this case, polySi(!:SiO□
By making the etching rates substantially equal, the side wall 4A can completely cover the side surface of the contact hole 3.

The RIE conditions for polySt include carbon tetrafluoride (
CF, ) and 02 are used, the pressure is reduced to 0.2 Torr, and a power of 350°C with a frequency of 13.56 MH2 is applied.

In FIG. 1 (3), high melting point metal,
For example, - is selectively grown to fill the inside of the contact hole 3. 5 is a selectively grown single layer.

-〇CVD conditions are the same as in the conventional example, using ridges, 1) 2 and 0□ as reaction gases, reducing the pressure to 0.5 Torr, and performing thermal decomposition at 320°C.

In this case, the layer 5 has a thickness of 1 μm due to growth from the side surface.
It is also easy to selectively grow the contact holes of a highly integrated device, which have a large depth compared to the diameter.

As described above, the contact hole planarization step is completed, and although not shown, an At layer, for example, is then deposited as a wiring layer over the entire surface of the substrate and patterned by photolithography to form a wiring pattern.

〔Effect of the invention〕

As explained in detail above, the selective growth of the high melting point metal according to the present invention can sufficiently fill the contact hole, thereby making it possible to flatten the substrate, contributing to higher integration, multilayering, and higher reliability of devices. can do.

[Brief explanation of drawings]

Figures 1 (1) to (3) are cross-sectional views illustrating the planarization process of burying a high melting point metal into a contact hole according to the present invention. Figure 2 is a planarization process of burying a high melting point metal into a contact hole according to a conventional example. It is a sectional view explaining a process. In the figure, 1 is the base St substrate, 2 is the insulating layer, SiO□ layer, 3 is the contact hole, 4 is the poly-Si layer, 4A is the side wall made of poly-Si, and 5 is the selectively grown single layer.

Claims (2)

[Claims] (1) An insulating layer (2) is deposited on the base (1), a contact hole (3) is formed in the insulating layer (2), and a polycrystalline silicon layer (4) is formed to cover the contact hole (3). ) and the contact hole (3) is formed by anisotropic etching with a predominance in the vertical direction.
forming a side wall (4A) made of the polycrystalline silicon layer (4) on the side surface of the insulating layer (2) in the contact hole (3), and selectively growing a refractory metal in the contact hole (3). A method for manufacturing a semiconductor device. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the base is a silicon (Si) substrate.